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Change subject: soc/intel/denverton_ns: enable Denverton to use common SoC XHCI code
......................................................................
Patch Set 11:
(1 comment)
Patchset:
PS11:
Please remove this unneeded commented include from chip.h
Beside above looks OK.
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Change subject: nb/amd/common: Move RAM calcualtion to common code
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61682/comment/8fab30e2_bb11dad1
PS4, Line 12: did
> do
Done
File src/northbridge/amd/agesa/family14/northbridge.c:
https://review.coreboot.org/c/coreboot/+/61682/comment/eb572c95_f52db3ca
PS4, Line 525: u64 basek, limitk, sizek; // 4 1T
> Please add a comment about the type changes in the commit message.
Done
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59807
to look at the new patch set (#16).
Change subject: nb/amd/agesa/family14: Enable PARALLEL_MP
......................................................................
nb/amd/agesa/family14: Enable PARALLEL_MP
Disable LEGACY_SMP_INIT and enable PARALLEL_MP.
TEST=Boot Debian 11 on PC Engines apu1
Boot time reduced by ~3ms on average.
Inspired by CB:59693
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
Change-Id: I39a0779bdf115eebe31290591152b920acde773e
---
M src/cpu/amd/agesa/family14/model_14_init.c
M src/northbridge/amd/agesa/family14/Kconfig
M src/northbridge/amd/agesa/family14/northbridge.c
3 files changed, 23 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/59807/16
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Michał Kopeć has uploaded a new patch set (#16) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/52781 )
Change subject: cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution
......................................................................
cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution
Create the correct MTRR solution based on the physical address space
provided by RESOURCE_ALLOCATOR_V4. Previously CPU initialization did not
account for lost C6 DRAM storage MTRR during postcar frame creation.
The BSP on 2GB has been stripped from UC MTRR covering C6 DRAM and
overlapping with usable DRAM WB MTRR. However this UC MTRR remained on
APs which caused inconsistent MTRRs warning in Linux. Use generic MTRR
function to create correct MTRR solution that propagates to APs. This
also fixes the inconsistent MTRRs warning.
TEST=boot Debian with Linux 4.14 on apu1 2GB
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: If706f8851ed0b1d45729e81175d82abb1d9193be
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M src/cpu/amd/agesa/family14/model_14_init.c
1 file changed, 16 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/52781/16
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Michał Kopeć has uploaded a new patch set (#12) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/52780 )
Change subject: northbridge/amd/agesa/family14: enable RESOURCE_ALLOCATOR_V4
......................................................................
northbridge/amd/agesa/family14: enable RESOURCE_ALLOCATOR_V4
TEST=boot Debian with Linux 4.14 on apu1 2GB
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: Ia01c5e238d53f719bb0d15e106517b99432a0c31
---
M src/northbridge/amd/agesa/family14/Kconfig
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/52780/12
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Michał Kopeć has uploaded a new patch set (#11) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/52935 )
Change subject: nb/amd/agesa/family14/northbridge.c: Report missing resources
......................................................................
nb/amd/agesa/family14/northbridge.c: Report missing resources
Not all resources were being reported, add them.
TEST=boot Debian with Linux 4.14 on apu1 2GB
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: I0b1b5f585ff6e0c7aecad250a75600e0c76331e1
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---
M src/northbridge/amd/agesa/family14/northbridge.c
1 file changed, 50 insertions(+), 46 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/52935/11
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Change subject: nb/amd/agesa/family14: Use generic allocation functions for PCI domain
......................................................................
nb/amd/agesa/family14: Use generic allocation functions for PCI domain
Move the DRAM reporting to read_resoures function before the resources
are being set. Use generic PCI domain resource allocation functions
to read and set domain resources.
TEST=boot Debian with Linux 4.14 on apu1 2GB
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: Ie322c7eee443646a5690920c1e06851ee5fdfac3
---
M src/northbridge/amd/agesa/family14/northbridge.c
1 file changed, 5 insertions(+), 59 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/53954/9
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Change subject: nb/amd/agesa/family14: Use generic allocation functions for northbridge
......................................................................
nb/amd/agesa/family14: Use generic allocation functions for northbridge
Remove obsolete resource assigning functions. IO and MMIO address
registers are currently set by amd_initcpuio to cover whole PCI hole
under 4G to MMIO and IO 0x0000-0xFFFF is configured to be routed to
southbridge already. Use generic PCI and resource allocation functions
wherever possible to set northbridge resources.
TEST=boot Debian with Linux 4.14 on apu1 2GB
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: I74a0ed1fcbbc9e066c42c4d51d30ab1d7138134a
---
M src/northbridge/amd/agesa/family14/northbridge.c
1 file changed, 7 insertions(+), 243 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/52934/9
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Change subject: nb/amd/common: Move RAM calcualtion to common code
......................................................................
nb/amd/common: Move RAM calcualtion to common code
This patch addresses post-merge comments from CB:52922. This change
unifies the code used by AMD northbridges, and changes the type of
basek, sizek, limitk to u64.
TEST=Boot PC Engines apu1 and see that RAM resources do not change.
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: I3d222f6cbd26fe78d968d2883984f25e8b62ab5c
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M src/northbridge/amd/agesa/family14/Makefile.inc
M src/northbridge/amd/agesa/family14/northbridge.c
M src/northbridge/amd/agesa/family15tn/Makefile.inc
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/northbridge/amd/agesa/family16kb/Makefile.inc
M src/northbridge/amd/agesa/family16kb/northbridge.c
A src/northbridge/amd/common/ram_calc.c
M src/northbridge/amd/nb_common.h
M src/northbridge/amd/pi/00730F01/Makefile.inc
M src/northbridge/amd/pi/00730F01/northbridge.c
10 files changed, 99 insertions(+), 137 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/61682/5
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Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63403 )
Change subject: util/intelp2m: Add support for Alder Lake macro generation
......................................................................
Patch Set 5:
(1 comment)
File util/intelp2m/platforms/adl/macro.go:
https://review.coreboot.org/c/coreboot/+/63403/comment/692e0040_fb0a0aa4
PS4, Line 52: var remapping = map[uint8]uint32{
> let's add RST_PWROK to the map? […]
If I'm not mistaken, RST_PWROK = Global Reset?
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