coreboot-gerrit April 2022

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Change in coreboot[master]: nb/amd/agesa/family14/northbridge.c: Report missing resources
by Michał Kopeć (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Nico Huber, Michał Żygowski, Paul Menzel, Angel Pons, Felix Held. Michał Kopeć has uploaded a new patch set (#12) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/52935 ) Change subject: nb/amd/agesa/family14/northbridge.c: Report missing resources ...................................................................... nb/amd/agesa/family14/northbridge.c: Report missing resources Not all resources were being reported, add them: 0xa0000 - 0xbffff: legacy VGA 0xc0000 - 0xfffff: option ROMs and SeaBIOS (if used) CC6 DRAM TEST=boot Debian with Linux 4.14 on apu1 2GB Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I0b1b5f585ff6e0c7aecad250a75600e0c76331e1 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/northbridge/amd/agesa/family14/northbridge.c 1 file changed, 50 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/52935/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/52935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b1b5f585ff6e0c7aecad250a75600e0c76331e1 Gerrit-Change-Number: 52935 Gerrit-PatchSet: 12 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/amd/agesa/family14: Enable PARALLEL_MP
by Michał Kopeć (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Michał Żygowski, Paul Menzel, Arthur Heymans. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59807 ) Change subject: nb/amd/agesa/family14: Enable PARALLEL_MP ...................................................................... Patch Set 16: (2 comments) File src/cpu/amd/agesa/family14/model_14_init.c: https://review.coreboot.org/c/coreboot/+/59807/comment/0248920f_5b10aaa7 PS16, Line 22: enable_cache(); > also done by the SIPI stub so remove. Done File src/northbridge/amd/agesa/family14/northbridge.c: https://review.coreboot.org/c/coreboot/+/59807/comment/3b815241_54bc34cb PS16, Line 311: if (acpi_is_wakeup_s3()) : restore_mtrr(); : else > remove. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39a0779bdf115eebe31290591152b920acde773e Gerrit-Change-Number: 59807 Gerrit-PatchSet: 16 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 12 Apr 2022 13:02:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: nb/amd/agesa/family14: Enable PARALLEL_MP
by Michał Kopeć (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Michał Żygowski, Michał Kopeć, Paul Menzel. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59807 to look at the new patch set (#17). Change subject: nb/amd/agesa/family14: Enable PARALLEL_MP ...................................................................... nb/amd/agesa/family14: Enable PARALLEL_MP Disable LEGACY_SMP_INIT and enable PARALLEL_MP. TEST=Boot Debian 11 on PC Engines apu1 Boot time reduced by ~3ms on average. Inspired by CB:59693 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Change-Id: I39a0779bdf115eebe31290591152b920acde773e Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/cpu/amd/agesa/family14/model_14_init.c M src/northbridge/amd/agesa/family14/Kconfig M src/northbridge/amd/agesa/family14/northbridge.c 3 files changed, 20 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/59807/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/59807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39a0779bdf115eebe31290591152b920acde773e Gerrit-Change-Number: 59807 Gerrit-PatchSet: 17 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/amd/common: Move RAM calcualtion to common code
by Arthur Heymans (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Nico Huber, Michał Żygowski, Paul Menzel, Michał Kopeć. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61682 ) Change subject: nb/amd/common: Move RAM calcualtion to common code ...................................................................... Patch Set 5: (3 comments) File src/northbridge/amd/common/ram_calc.c: https://review.coreboot.org/c/coreboot/+/61682/comment/82817812_8930c9d8 PS5, Line 28: > Should this be >= ? https://review.coreboot.org/c/coreboot/+/61682/comment/72dea7b8_cb083e26 PS5, Line 42: nit: double spaces. https://review.coreboot.org/c/coreboot/+/61682/comment/e4c37359_bdc8e48a PS5, Line 50: *limitk += 1; /* round up last byte for northbridge resource calculation convenience */ : *limitk /= KiB; /* Normalize to KiB */ I think you need /= KiB first and then += 1. -- To view, visit https://review.coreboot.org/c/coreboot/+/61682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d222f6cbd26fe78d968d2883984f25e8b62ab5c Gerrit-Change-Number: 61682 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 13:01:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/starlabs/lite: Change PMC from hidden to on
by Stephen Edworthy (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Stephen Edworthy. Stephen Edworthy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63404 ) Change subject: mb/starlabs/lite: Change PMC from hidden to on ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/63404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cf1be7f6919d974614f2196a0eb611cc40abe3d Gerrit-Change-Number: 63404 Gerrit-PatchSet: 1 Gerrit-Owner: Stephen Edworthy <stephen(a)starlabs.org.uk> Gerrit-Reviewer: Stephen Edworthy <stephen(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stephen Edworthy <stephen(a)starlabs.systems> Gerrit-Comment-Date: Tue, 12 Apr 2022 12:58:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/xhci: Add function to reset the XHCI controller
by Subrata Banik (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Tim Wawrzynczak. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63551 to look at the new patch set (#3). Change subject: soc/intel/cmn/xhci: Add function to reset the XHCI controller ...................................................................... soc/intel/cmn/xhci: Add function to reset the XHCI controller This patch adds `xhci_host_reset()` to reset XHCI controller and the scope of this function is with SMM hence, compiling xhci.c for SMM as well. Also, refactored `xhci.c` code to keep PCI enumeration within the scope of `ramstage` alone hence, guarded with `ENV_RAMSTAGE` env_variable. BUG=b:227289581 TEST=Able to perform a call from `xhci_host_reset` from S5 smi handler. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ie0dc0a64044f291893931726d26c08c8b964a3cc --- M src/soc/intel/common/block/include/intelblocks/xhci.h M src/soc/intel/common/block/xhci/Makefile.inc M src/soc/intel/common/block/xhci/xhci.c 3 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/63551/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0dc0a64044f291893931726d26c08c8b964a3cc Gerrit-Change-Number: 63551 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/amd/agesa/family14: Enable PARALLEL_MP
by Arthur Heymans (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Michał Żygowski, Michał Kopeć, Paul Menzel. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59807 ) Change subject: nb/amd/agesa/family14: Enable PARALLEL_MP ...................................................................... Patch Set 16: (3 comments) File src/cpu/amd/agesa/family14/model_14_init.c: https://review.coreboot.org/c/coreboot/+/59807/comment/2fb26800_a4dcc271 PS16, Line 22: enable_cache(); also done by the SIPI stub so remove. File src/northbridge/amd/agesa/family14/northbridge.c: https://review.coreboot.org/c/coreboot/+/59807/comment/7df7f8bd_2760b4e5 PS16, Line 311: if (acpi_is_wakeup_s3()) : restore_mtrr(); : else remove. https://review.coreboot.org/c/coreboot/+/59807/comment/b94c747a_57efe9dd PS16, Line 321: uint8_t siblings = cpuid_ecx(0x80000008) & 0xff; : : return siblings + 1; Should this change? It looks like most other AMD code does read this from the PCI config space. -- To view, visit https://review.coreboot.org/c/coreboot/+/59807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39a0779bdf115eebe31290591152b920acde773e Gerrit-Change-Number: 59807 Gerrit-PatchSet: 16 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 12 Apr 2022 12:45:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/denverton_ns: enable Denverton to use common SoC SPI code
by Mariusz Szafrański (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Jeff Daly, Suresh Bellampalli, Patrick Rudolph. Mariusz Szafrański has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61014 ) Change subject: soc/intel/denverton_ns: enable Denverton to use common SoC SPI code ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1d57c6b348adb934785b0e2bec4e856f0bf8d77 Gerrit-Change-Number: 61014 Gerrit-PatchSet: 10 Gerrit-Owner: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 12 Apr 2022 12:42:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution
by Arthur Heymans (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Michał Żygowski, Michał Kopeć. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52781 ) Change subject: cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution ...................................................................... Patch Set 16: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If706f8851ed0b1d45729e81175d82abb1d9193be Gerrit-Change-Number: 52781 Gerrit-PatchSet: 16 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 12:42:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/xhci: Add function to reset the XHCI controller
by Subrata Banik (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63551 ) Change subject: soc/intel/cmn/xhci: Add function to reset the XHCI controller ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/xhci/xhci.c: https://review.coreboot.org/c/coreboot/+/63551/comment/f3d3d390_b2ba2d2e PS2, Line 30: 0xf > `PCI_BASE_ADDRESS_MEM_MASK` Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/63551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0dc0a64044f291893931726d26c08c8b964a3cc Gerrit-Change-Number: 63551 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 12 Apr 2022 12:42:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit April 2022