coreboot-gerrit April 2022

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Change in coreboot[master]: superio/smsc/mec1308: Drop `_PRS` from static devices
by Felix Held (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Angel Pons, Arthur Heymans. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63523 ) Change subject: superio/smsc/mec1308: Drop `_PRS` from static devices ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d5cdc28c2cfaa5dfcffd656060b931208977386 Gerrit-Change-Number: 63523 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 20 Apr 2022 10:02:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: superio/smsc/sch5545: Drop `_PRS` from static devices
by Felix Held (Code Review) 20 Apr '22

20 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63522 ) Change subject: superio/smsc/sch5545: Drop `_PRS` from static devices ...................................................................... superio/smsc/sch5545: Drop `_PRS` from static devices The `_PRS` ACPI object is not needed for static (non-configurable) devices. For devices where `_CRS` always provides the same set of resource settings, drop the `_PRS` object. Note that every dropped `_PRS` object only provides one set of resource settings, which is identical to the resource settings provided by the `_CRS` object. In addition, drop `IGNORE_IASL_MISSING_DEPENDENCY` from the only mainboard using the SCH5545 code, `dell/snb_ivb_workstations`. Change-Id: Ic462bd3dfa287744d4f733561de81c09c1c397e6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63522 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/dell/snb_ivb_workstations/Kconfig M src/superio/smsc/sch5545/acpi/superio.asl 2 files changed, 0 insertions(+), 28 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/dell/snb_ivb_workstations/Kconfig b/src/mainboard/dell/snb_ivb_workstations/Kconfig index 8416a0f..788f5a1 100644 --- a/src/mainboard/dell/snb_ivb_workstations/Kconfig +++ b/src/mainboard/dell/snb_ivb_workstations/Kconfig @@ -20,9 +20,6 @@ if BOARD_DELL_SNB_IVB_WORKSTATIONS -config IGNORE_IASL_MISSING_DEPENDENCY - def_bool y - config MAINBOARD_DIR default "dell/snb_ivb_workstations" diff --git a/src/superio/smsc/sch5545/acpi/superio.asl b/src/superio/smsc/sch5545/acpi/superio.asl index 97303c2..20278b4 100644 --- a/src/superio/smsc/sch5545/acpi/superio.asl +++ b/src/superio/smsc/sch5545/acpi/superio.asl @@ -232,22 +232,6 @@ ) IRQ (Edge, ActiveHigh, Exclusive) {1} }) - Name (_PRS, ResourceTemplate () - { - StartDependentFn (0x00, 0x00) - { - FixedIO ( - 0x0060, // Address - 0x01, - ) - FixedIO ( - 0x0064, // Address - 0x01, - ) - IRQ (Edge, ActiveHigh, Exclusive) {1} - } - EndDependentFn () - }) Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake { KBFG = Arg0 @@ -268,15 +252,6 @@ IRQ (Edge, ActiveHigh, Exclusive) {12} }) - Name (_PRS, ResourceTemplate () - { - StartDependentFn (0x00, 0x00) - { - IRQ (Edge, ActiveHigh, Exclusive) {12} - } - EndDependentFn () - }) - Method (_PSW, 1, NotSerialized) { MSFG = Arg0 -- To view, visit https://review.coreboot.org/c/coreboot/+/63522 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic462bd3dfa287744d4f733561de81c09c1c397e6 Gerrit-Change-Number: 63522 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: superio/smsc/sch5545: Drop `_PRS` from static devices
by Felix Held (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Michał Żygowski, Michał Kopeć, Angel Pons. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63522 ) Change subject: superio/smsc/sch5545: Drop `_PRS` from static devices ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63522 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic462bd3dfa287744d4f733561de81c09c1c397e6 Gerrit-Change-Number: 63522 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 20 Apr 2022 10:01:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/kontron/986lcd-m: Drop `_PRS` and `_DIS` from static devices
by Felix Held (Code Review) 20 Apr '22

20 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63524 ) Change subject: mb/kontron/986lcd-m: Drop `_PRS` and `_DIS` from static devices ...................................................................... mb/kontron/986lcd-m: Drop `_PRS` and `_DIS` from static devices The `_PRS` ACPI object is not needed for static (non-configurable) devices. For devices where `_CRS` always provides the same set of resource settings, drop the `_PRS` object. Note that every dropped `_PRS` object only provides one set of resource settings, which is identical to the resource settings provided by the `_CRS` object. The no-op `_DIS` methods can also be removed for the same reason. Also, drop `IGNORE_IASL_MISSING_DEPENDENCY` as it's no longer needed. Change-Id: I71275f2581b999d606f36773578b36dbdccf6452 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63524 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/kontron/986lcd-m/Kconfig M src/mainboard/kontron/986lcd-m/acpi/superio.asl 2 files changed, 0 insertions(+), 21 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index dc07949..e8407de 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -1,8 +1,5 @@ if BOARD_KONTRON_986LCD_M -config IGNORE_IASL_MISSING_DEPENDENCY - def_bool y - config BOARD_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_SOCKET_M diff --git a/src/mainboard/kontron/986lcd-m/acpi/superio.asl b/src/mainboard/kontron/986lcd-m/acpi/superio.asl index 488bf18..1932eab 100644 --- a/src/mainboard/kontron/986lcd-m/acpi/superio.asl +++ b/src/mainboard/kontron/986lcd-m/acpi/superio.asl @@ -18,15 +18,6 @@ Return (0x0f) } - Method (_DIS, 0) { /* NOOP */ } - - Name (_PRS, ResourceTemplate() { - StartDependentFn(0, 1) { - IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) - IRQNoFlags() { 4 } - } EndDependentFn() - }) - Method (_CRS, 0) { Return(ResourceTemplate() { @@ -51,15 +42,6 @@ Return (0x0f) } - Method (_DIS, 0) { /* NOOP */ } - - Name (_PRS, ResourceTemplate() { - StartDependentFn(0, 1) { - IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) - IRQNoFlags() { 3 } - } EndDependentFn() - }) - Method (_CRS, 0) { Return(ResourceTemplate() { 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71275f2581b999d606f36773578b36dbdccf6452 Gerrit-Change-Number: 63524 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/dptf: Add support for PROP method
by Felix Held (Code Review) 20 Apr '22

20 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63697 ) Change subject: drivers/intel/dptf: Add support for PROP method ...................................................................... drivers/intel/dptf: Add support for PROP method Add PROP method under \_SB.DPTF.TPWR scope which will return static worst case rest of platform power in miliWatts. This value is static, which has to configured from devicetree of overridetree for each platform BUG=b:205928013 TEST=Build, boot brya0 and dump SSDT to check PROP method Scope (\_SB) { Device (DPTF) { Device (TPWR) { Method (PROP, 0, Serialized) { Return (XXXX) } } } } Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I1415d2a9eb55cfadc3a7b41b53ecbec657002759 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63697 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/drivers/intel/dptf/chip.h M src/drivers/intel/dptf/dptf.c 2 files changed, 17 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/drivers/intel/dptf/chip.h b/src/drivers/intel/dptf/chip.h index 59b1e25..060f196 100644 --- a/src/drivers/intel/dptf/chip.h +++ b/src/drivers/intel/dptf/chip.h @@ -59,6 +59,9 @@ struct { uint32_t oem_variables[DPTF_OEM_VARIABLE_COUNT]; } oem_data; + + /* Rest of platform Power */ + uint32_t prop; }; #endif /* _DRIVERS_INTEL_DPTF_CHIP_H_ */ diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c index 27c7133..3cfd23c 100644 --- a/src/drivers/intel/dptf/dptf.c +++ b/src/drivers/intel/dptf/dptf.c @@ -372,7 +372,8 @@ acpigen_write_device_end(); /* TPCH Device */ } -static void write_create_tpwr(const struct dptf_platform_info *platform_info) +static void write_create_tpwr(const struct drivers_intel_dptf_config *config, + const struct dptf_platform_info *platform_info) { acpigen_write_device("TPWR"); acpigen_write_name("_HID"); @@ -382,12 +383,21 @@ acpigen_write_name_string("_STR", DEFAULT_POWER_STR); acpigen_write_name_integer("PTYP", DPTF_GENERIC_PARTICIPANT_TYPE_POWER); acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + + /* PROP method */ + if(config->prop != 0) { + acpigen_write_method_serialized("PROP", 0); + acpigen_emit_byte(RETURN_OP); + acpigen_write_integer(config->prop); + acpigen_pop_len(); /* Method PROP */ + } acpigen_write_device_end(); /* TPWR Power Participant Device */ } -static void write_tpwr_methods(const struct dptf_platform_info *platform_info) +static void write_tpwr_methods(const struct drivers_intel_dptf_config *config, + const struct dptf_platform_info *platform_info) { - write_create_tpwr(platform_info); + write_create_tpwr(config, platform_info); } static void write_create_tbat(const struct dptf_platform_info *platform_info) @@ -449,7 +459,7 @@ write_tpch_methods(platform_info); if (CONFIG(DRIVERS_INTEL_DPTF_SUPPORTS_TPWR)) - write_tpwr_methods(platform_info); + write_tpwr_methods(config, platform_info); if (CONFIG(DRIVERS_INTEL_DPTF_SUPPORTS_TBAT)) write_tbat_methods(platform_info); -- To view, visit https://review.coreboot.org/c/coreboot/+/63697 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1415d2a9eb55cfadc3a7b41b53ecbec657002759 Gerrit-Change-Number: 63697 Gerrit-PatchSet: 5 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Poornima Tom <poornima.tom(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/skyrim: Configure SD card
by Ian Feng (Code Review) 20 Apr '22

20 Apr '22

Ian Feng has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/63739 ) Change subject: mb/google/skyrim: Configure SD card ...................................................................... mb/google/skyrim: Configure SD card Add power sequence. BUG=b:229181624 TEST=Build and boot to OS in Skyrim. Ensure that the SD Controller and SD Card are enumerated fine. 02:00.0 SD Host controller: Genesys Logic, Inc GL9750 (rev 01) Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Change-Id: I03d88d90acc03cdebcb1e83ed2e799dda8b5b735 --- M src/mainboard/google/skyrim/variants/baseboard/gpio.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/63739/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63739 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03d88d90acc03cdebcb1e83ed2e799dda8b5b735 Gerrit-Change-Number: 63739 Gerrit-PatchSet: 3 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/skyrim: Configure SD card sequence
by Ian Feng (Code Review) 20 Apr '22

20 Apr '22

Ian Feng has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/63739 ) Change subject: mb/google/skyrim: Configure SD card sequence ...................................................................... mb/google/skyrim: Configure SD card sequence Add power sequence. BUG=b:229181624 TEST=Build and boot to OS in Skyrim. Ensure that the SD Controller and SD Card are enumerated fine. 02:00.0 SD Host controller: Genesys Logic, Inc GL9750 (rev 01) Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Change-Id: I03d88d90acc03cdebcb1e83ed2e799dda8b5b735 --- M src/mainboard/google/skyrim/variants/baseboard/gpio.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/63739/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63739 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03d88d90acc03cdebcb1e83ed2e799dda8b5b735 Gerrit-Change-Number: 63739 Gerrit-PatchSet: 2 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Implement PMC feature lock
by Subrata Banik (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Eric Lai, Lean Sheng Tan, Werner Zeh. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63691 ) Change subject: soc/intel/alderlake: Implement PMC feature lock ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/alderlake/lockdown.c: https://review.coreboot.org/c/coreboot/+/63691/comment/d7de6e5a_99db8cc4 PS4, Line 28: setbits32(pmc_mmio_regs() + PM_CFG, PM_CFG_DBG_MODE_LOCK | > Yes, this is what I mean. And we can use #ifdef CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM) in structure, to make it optimize in built time. I don't expect it will be a lot need to skip. Line#25 if possible to convert into `#if` clause but what about line#22, chipset_lockdown value is not known during compilation time. -- To view, visit https://review.coreboot.org/c/coreboot/+/63691 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29178bdd9a94a24ca7056eb7377625f41a43c33c Gerrit-Change-Number: 63691 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Wed, 20 Apr 2022 09:48:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/skyrim: Configure SD card sequence
by Ian Feng (Code Review) 20 Apr '22

20 Apr '22

Ian Feng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63739 ) Change subject: mb/google/skyrim: Configure SD card sequence ...................................................................... mb/google/skyrim: Configure SD card sequence Add power sequence according to datasheet: GL9750S-OIY04 rev1.22. BUG=b:229181624 TEST=Build and boot to OS in Skyrim. Ensure that the SD Controller and SD Card are enumerated fine. 02:00.0 SD Host controller: Genesys Logic, Inc GL9750 (rev 01) Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Change-Id: I03d88d90acc03cdebcb1e83ed2e799dda8b5b735 --- M src/mainboard/google/skyrim/variants/baseboard/gpio.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/63739/1 diff --git a/src/mainboard/google/skyrim/variants/baseboard/gpio.c b/src/mainboard/google/skyrim/variants/baseboard/gpio.c index 6ff2906..9131329 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/gpio.c +++ b/src/mainboard/google/skyrim/variants/baseboard/gpio.c @@ -186,6 +186,8 @@ /* Power on WLAN */ /* EN_PP3300_WLAN */ PAD_GPO(GPIO_9, HIGH), + /* SD_AUX_RESET_L */ + PAD_GPO(GPIO_27, LOW), }; /* PCIE_RST needs to be brought high before FSP-M runs */ @@ -195,6 +197,8 @@ PAD_GPO(GPIO_7, HIGH), /* PCIE_RST0_L */ PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), + /* SD_AUX_RESET_L */ + PAD_GPO(GPIO_27, HIGH), }; __weak void variant_pcie_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) -- To view, visit https://review.coreboot.org/c/coreboot/+/63739 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03d88d90acc03cdebcb1e83ed2e799dda8b5b735 Gerrit-Change-Number: 63739 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: docs/coding_style: Clarify use of GCC extensions
by Felix Held (Code Review) 20 Apr '22

20 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63660 ) Change subject: docs/coding_style: Clarify use of GCC extensions ...................................................................... docs/coding_style: Clarify use of GCC extensions This patch adds a section to the coding style that explicitly clarifies the use of GCC extensions in coreboot (which has been long-standing practice anyway), and expressly allows their use. See the mailing list discussion for more details: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/3C2Q… Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I0d0eb90d6729fefeb131cdd573ad51f1884afe11 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63660 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> --- M Documentation/contributing/coding_style.md 1 file changed, 35 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified David Hendricks: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved Krystian Hebel: Looks good to me, but someone else must approve Yu-Ping Wu: Looks good to me, but someone else must approve diff --git a/Documentation/contributing/coding_style.md b/Documentation/contributing/coding_style.md index 6564545..3314030 100644 --- a/Documentation/contributing/coding_style.md +++ b/Documentation/contributing/coding_style.md @@ -960,6 +960,41 @@ : /* outputs */ : /* inputs */ : /* clobbers */); ``` +GCC extensions +-------------- + +GCC is the only officially-supported compiler for coreboot, and a +variety of its C language extensions are heavily used throughout the +code base. There have been occasional attempts to add clang as a second +compiler option, which is generally compatible to the same language +extensions that have been long-established by GCC. + +Some GCC extensions (e.g. inline assembly) are basically required for +proper firmware development. Others enable more safe or flexible +coding patterns than can be expressed with standard C (e.g. statement +expressions and `typeof()` to avoid double evaluation in macros like +`MAX()`). Yet others just add some simple convenience and reduce +boilerplate (e.g. `void *` arithmetic). + +Since some GCC extensions are necessary either way, there is no gain +from avoiding other GCC extensions elsewhere. The use of all official +GCC extensions is expressly allowed within coreboot. In cases where an +extension can be replaced by a 100% equivalent C standard feature with +no extra boilerplate or loss of readability, the C standard feature +should be preferred (this usually only happens when GCC retains an +older pre-standardization extension for backwards compatibility, e.g. +the old pre-C99 syntax for designated initializers). But if there is +any advantage offered by the GCC extension (e.g. using GCC zero-length +arrays instead of C99 variable-length arrays because they don't inhibit +`sizeof()`), there is no reason to deprive ourselves of that, and "this +is not C standard compliant" should not be a reason to argue against +its use in reviews. + +This rule only applies to explicit GCC extensions listed in the +"Extensions to the C Language Family" section of the GCC manual. Code +should never rely on incidental GCC translation behavior that is not +explicitly documented as a feature and could change at any moment. + References ---------- -- To view, visit https://review.coreboot.org/c/coreboot/+/63660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d0eb90d6729fefeb131cdd573ad51f1884afe11 Gerrit-Change-Number: 63660 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit April 2022