Attention is currently required from: Ariel Fang, YH Lin, Subrata Banik, Paul Menzel, Eric Lai, Raihow Shi, Felix Held.
Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63080 )
Change subject: mb/google/brask/variants/moli: update overridetree
......................................................................
Patch Set 22: Code-Review+2
--
To view, visit https://review.coreboot.org/c/coreboot/+/63080
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If83031edcd90ea746704590765102b9b0dee03c1
Gerrit-Change-Number: 63080
Gerrit-PatchSet: 22
Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com>
Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: YH Lin <yueherngl(a)google.com>
Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com>
Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com>
Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com>
Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com>
Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com>
Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com>
Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com>
Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com>
Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com>
Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com>
Gerrit-Attention: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com>
Gerrit-Attention: YH Lin <yueherngl(a)google.com>
Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Gerrit-Attention: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com>
Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Comment-Date: Wed, 20 Apr 2022 14:12:49 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: Yes
Gerrit-MessageType: comment
Attention is currently required from: Arthur Heymans.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63711 )
Change subject: lib/coreboot_table.c: Use align macro
......................................................................
Patch Set 3: Code-Review+2
--
To view, visit https://review.coreboot.org/c/coreboot/+/63711
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie874fe2c023157fad0adc021faa45e70822208da
Gerrit-Change-Number: 63711
Gerrit-PatchSet: 3
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Comment-Date: Wed, 20 Apr 2022 14:03:25 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: Yes
Gerrit-MessageType: comment
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63741 )
Change subject: [UNTESTED] soc/amd/sabrina: enable warm reset functionality
......................................................................
[UNTESTED] soc/amd/sabrina: enable warm reset functionality
Commit 3e1943ec46d04aff01c7fc755ac371e33e7a2dcb (soc/amd/cezanne: Force
resets to be cold) forced all resets on Cezanne to be cold resets to
work around a bug. Since the bug is fixed on Sabrina, this workaround
copied over from the Cezanne code isn't needed here, so sort-of revert
what the patch referenced above changed for Cezanne in the Sabrina code.
BUG=b:229105416
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I785e43124a9a969eeb129454e6e15dc245625250
---
M src/soc/amd/sabrina/fch.c
M src/soc/amd/sabrina/reset.c
2 files changed, 1 insertion(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/63741/1
diff --git a/src/soc/amd/sabrina/fch.c b/src/soc/amd/sabrina/fch.c
index 9be7dd8..a768989 100644
--- a/src/soc/amd/sabrina/fch.c
+++ b/src/soc/amd/sabrina/fch.c
@@ -127,11 +127,6 @@
PM_ACPI_TIMER_EN_EN);
}
-static void fch_init_resets(void)
-{
- pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD);
-}
-
/* configure the general purpose PCIe clock outputs according to the devicetree settings */
static void gpp_clk_setup(void)
{
@@ -198,7 +193,6 @@
void fch_init(void *chip_info)
{
- fch_init_resets();
i2c_soc_init();
fch_init_acpi_ports();
diff --git a/src/soc/amd/sabrina/reset.c b/src/soc/amd/sabrina/reset.c
index 90fedda..28e60b6 100644
--- a/src/soc/amd/sabrina/reset.c
+++ b/src/soc/amd/sabrina/reset.c
@@ -19,9 +19,7 @@
void do_warm_reset(void)
{
- /* Warm resets are not supported and must be executed as cold */
- pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) |
- TOGGLE_ALL_PWR_GOOD);
+ /* Assert reset signals only. */
outb(RST_CPU | SYS_RST, RST_CNT);
}
--
To view, visit https://review.coreboot.org/c/coreboot/+/63741
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I785e43124a9a969eeb129454e6e15dc245625250
Gerrit-Change-Number: 63741
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-MessageType: newchange
Attention is currently required from: Sridhar Siricilla.
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63734
to look at the new patch set (#3).
Change subject: soc/intel/common: Fix buggy code tries to access DESC region
......................................................................
soc/intel/common: Fix buggy code tries to access DESC region
The patch fixes the buggy code which tries to access the Descriptor
Region. The existing code doesn't use correct APIs to access the
Descriptor Region. Hence, error message is getting displayed during
the boot.
TEST=Build and verify no errors seen while accessing the Descriptor
Region.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: Ib144cc0845b7527e5a3032529b0802f961944b87
---
M src/soc/intel/common/basecode/debug/debug_feature.c
1 file changed, 3 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/63734/3
--
To view, visit https://review.coreboot.org/c/coreboot/+/63734
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib144cc0845b7527e5a3032529b0802f961944b87
Gerrit-Change-Number: 63734
Gerrit-PatchSet: 3
Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Gerrit-MessageType: newpatchset
Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Lean Sheng Tan, Werner Zeh.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63691 )
Change subject: soc/intel/alderlake: Implement PMC feature lock
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63691/comment/e0622517_2d10e7e5
PS4, Line 10: read access to PMC XRAM.
> > Why should that be locked? Should it be build-time configurable?
>
> it's firmware security guideline for alderlake
Alder Lake FAS Security Chapter 12
OS/payload shouldn't have access to PMC XRAM registers
--
To view, visit https://review.coreboot.org/c/coreboot/+/63691
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I29178bdd9a94a24ca7056eb7377625f41a43c33c
Gerrit-Change-Number: 63691
Gerrit-PatchSet: 4
Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com>
Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Comment-Date: Wed, 20 Apr 2022 11:33:01 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>
Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-MessageType: comment
Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Lean Sheng Tan, Werner Zeh.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63691 )
Change subject: soc/intel/alderlake: Implement PMC feature lock
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63691/comment/6a5382ce_a703c356
PS4, Line 10: read access to PMC XRAM.
> Why should that be locked? Should it be build-time configurable?
it's firmware security guideline for alderlake
--
To view, visit https://review.coreboot.org/c/coreboot/+/63691
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I29178bdd9a94a24ca7056eb7377625f41a43c33c
Gerrit-Change-Number: 63691
Gerrit-PatchSet: 4
Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com>
Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Comment-Date: Wed, 20 Apr 2022 11:29:05 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-MessageType: comment