coreboot-gerrit April 2022

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Change in coreboot[master]: mb/google/brya/var/craask: Generate SPD ID for supported memory part
by Tyler Wang (Code Review) 20 Apr '22

20 Apr '22

Tyler Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63738 ) Change subject: mb/google/brya/var/craask: Generate SPD ID for supported memory part ...................................................................... mb/google/brya/var/craask: Generate SPD ID for supported memory part Add supported memory parts in mem_parts_used.txt, and generate SPD id for this part. MT62F512M32D2DR-031 WT:B BUG=None TEST=None Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Change-Id: I183b74e66786c378cc227ee1e53ea422986b672a --- M src/mainboard/google/brya/variants/craask/memory/Makefile.inc M src/mainboard/google/brya/variants/craask/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/craask/memory/mem_parts_used.txt 3 files changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/63738/1 diff --git a/src/mainboard/google/brya/variants/craask/memory/Makefile.inc b/src/mainboard/google/brya/variants/craask/memory/Makefile.inc index eace2e4..247a1bc 100644 --- a/src/mainboard/google/brya/variants/craask/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/craask/memory/Makefile.inc @@ -1,5 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/craask/memory src/mainboard/google/brya/variants/craask/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B diff --git a/src/mainboard/google/brya/variants/craask/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/craask/memory/dram_id.generated.txt index fa24790..e3b10a0 100644 --- a/src/mainboard/google/brya/variants/craask/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/craask/memory/dram_id.generated.txt @@ -1 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/craask/memory src/mainboard/google/brya/variants/craask/memory/mem_parts_used.txt + DRAM Part Name ID to assign +MT62F512M32D2DR-031 WT:B 0 (0000) diff --git a/src/mainboard/google/brya/variants/craask/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/craask/memory/mem_parts_used.txt index 9621137..d1e64f1 100644 --- a/src/mainboard/google/brya/variants/craask/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/craask/memory/mem_parts_used.txt @@ -9,3 +9,4 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name +MT62F512M32D2DR-031 WT:B -- To view, visit https://review.coreboot.org/c/coreboot/+/63738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I183b74e66786c378cc227ee1e53ea422986b672a Gerrit-Change-Number: 63738 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: clean up dmi driver code
by Felix Held (Code Review) 20 Apr '22

20 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63472 ) Change subject: soc/intel: clean up dmi driver code ...................................................................... soc/intel: clean up dmi driver code 1. Remove dmi.h as it's migrated as gpmr.header 2. Remove unused gpmr definitions 3. For old platforms, define DMI defintions in c code for less code changes. TEST=Build Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: Ib340ff1ab7fd88b1e7b3860ffec055a75e562de7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63472 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/ocp/deltalake/bootblock.c M src/soc/intel/alderlake/bootblock/pch.c M src/soc/intel/cannonlake/bootblock/pch.c D src/soc/intel/common/block/include/intelblocks/dmi.h M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/elkhartlake/bootblock/pch.c M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/jasperlake/bootblock/pch.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/tigerlake/bootblock/pch.c M src/soc/intel/xeon_sp/pch.c 11 files changed, 4 insertions(+), 65 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/ocp/deltalake/bootblock.c b/src/mainboard/ocp/deltalake/bootblock.c index 402b572..46d7e70 100644 --- a/src/mainboard/ocp/deltalake/bootblock.c +++ b/src/mainboard/ocp/deltalake/bootblock.c @@ -13,6 +13,8 @@ #include <cpxsp_dl_gpio.h> #define ASPEED_SIO_PORT 0x2E +#define PCR_DMI_LPCIOD 0x2770 +#define PCR_DMI_LPCIOE 0x2774 static void enable_espi_lpc_io_windows(void) { diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c index bd204cd..893956b 100644 --- a/src/soc/intel/alderlake/bootblock/pch.c +++ b/src/soc/intel/alderlake/bootblock/pch.c @@ -9,7 +9,6 @@ #include <device/mmio.h> #include <device/device.h> #include <device/pci_ops.h> -#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -39,11 +38,6 @@ #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C -#define PCR_DMI_ACPIBA 0x27B4 -#define PCR_DMI_ACPIBDID 0x27B8 -#define PCR_DMI_PMBASEA 0x27AC -#define PCR_DMI_PMBASEC 0x27B0 - static void soc_config_pwrmbase(void) { /* diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index a4f47c9..7651cdf 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -4,7 +4,6 @@ #include <device/mmio.h> #include <device/device.h> #include <device/pci_ops.h> -#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gpio.h> #include <intelblocks/gspi.h> @@ -34,11 +33,6 @@ #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C -#define PCR_DMI_ACPIBA 0x27B4 -#define PCR_DMI_ACPIBDID 0x27B8 -#define PCR_DMI_PMBASEA 0x27AC -#define PCR_DMI_PMBASEC 0x27B0 - static uint32_t get_pmc_reg_base(void) { if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) diff --git a/src/soc/intel/common/block/include/intelblocks/dmi.h b/src/soc/intel/common/block/include/intelblocks/dmi.h deleted file mode 100644 index 8b12602..0000000 --- a/src/soc/intel/common/block/include/intelblocks/dmi.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef SOC_INTEL_COMMON_BLOCK_DMI_H -#define SOC_INTEL_COMMON_BLOCK_DMI_H - -#include <types.h> - -#define PCR_DMI_DMICTL 0x2234 -#define PCR_DMI_DMICTL_SRLOCK (1 << 31) - -#define PCR_DMI_GCS 0x274C -#define PCR_DMI_GCS_BILD (1 << 0) - -/* - * Takes base, size and destination ID and configures the GPMR - * for accessing the region. - */ -enum cb_err dmi_enable_gpmr(uint32_t base, uint32_t size, uint32_t dest_id); - -#endif /* SOC_INTEL_COMMON_BLOCK_DMI_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h index 43a3001..3590852 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h +++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h @@ -25,13 +25,6 @@ #define LPC_IOE_COMA_EN (1 << 0) #define LPC_NUM_GENERIC_IO_RANGES 4 -#define PCR_DMI_LPCLGIR1 0x2730 - -#define PCR_DMI_LPCGMR 0x2740 - -#define PCR_DMI_LPCIOD 0x2770 -#define PCR_DMI_LPCIOE 0x2774 - /* LPC PCR configuration */ #define PCR_LPC_PRC 0x341c #define PCR_LPC_CCE_EN 0xf diff --git a/src/soc/intel/elkhartlake/bootblock/pch.c b/src/soc/intel/elkhartlake/bootblock/pch.c index 09b78be..306908f 100644 --- a/src/soc/intel/elkhartlake/bootblock/pch.c +++ b/src/soc/intel/elkhartlake/bootblock/pch.c @@ -5,7 +5,6 @@ #include <device/device.h> #include <device/mmio.h> #include <device/pci_ops.h> -#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -32,11 +31,6 @@ #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C -#define PCR_DMI_ACPIBA 0x27B4 -#define PCR_DMI_ACPIBDID 0x27B8 -#define PCR_DMI_PMBASEA 0x27AC -#define PCR_DMI_PMBASEC 0x27B0 - static void soc_config_pwrmbase(void) { /* diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index 7694a10..7ab7ed9a 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -3,7 +3,6 @@ #include <device/mmio.h> #include <device/device.h> #include <device/pci_ops.h> -#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -28,11 +27,6 @@ #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C -#define PCR_DMI_ACPIBA 0x27B4 -#define PCR_DMI_ACPIBDID 0x27B8 -#define PCR_DMI_PMBASEA 0x27AC -#define PCR_DMI_PMBASEC 0x27B0 - static void soc_config_pwrmbase(void) { /* diff --git a/src/soc/intel/jasperlake/bootblock/pch.c b/src/soc/intel/jasperlake/bootblock/pch.c index a3c338e..4de63f2 100644 --- a/src/soc/intel/jasperlake/bootblock/pch.c +++ b/src/soc/intel/jasperlake/bootblock/pch.c @@ -5,7 +5,6 @@ #include <device/mmio.h> #include <device/device.h> #include <device/pci_ops.h> -#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -32,11 +31,6 @@ #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C -#define PCR_DMI_ACPIBA 0x27B4 -#define PCR_DMI_ACPIBDID 0x27B8 -#define PCR_DMI_PMBASEA 0x27AC -#define PCR_DMI_PMBASEC 0x27B0 - static void soc_config_pwrmbase(void) { /* diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index ec60cab..cc2d384 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -2,7 +2,6 @@ #include <device/pci_ops.h> #include <device/device.h> #include <device/pci_def.h> -#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <intelblocks/itss.h> diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 7351492..9758dba 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -11,7 +11,6 @@ #include <device/device.h> #include <device/mmio.h> #include <device/pci_ops.h> -#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -42,11 +41,6 @@ #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C -#define PCR_DMI_ACPIBA 0x27B4 -#define PCR_DMI_ACPIBDID 0x27B8 -#define PCR_DMI_PMBASEA 0x27AC -#define PCR_DMI_PMBASEC 0x27B0 - static void soc_config_pwrmbase(void) { /* diff --git a/src/soc/intel/xeon_sp/pch.c b/src/soc/intel/xeon_sp/pch.c index d2496b1..a8f47d3 100644 --- a/src/soc/intel/xeon_sp/pch.c +++ b/src/soc/intel/xeon_sp/pch.c @@ -3,7 +3,6 @@ #include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> -#include <intelblocks/dmi.h> #include <intelblocks/pcr.h> #include <intelblocks/rtc.h> #include <intelblocks/p2sb.h> @@ -14,6 +13,8 @@ #define PCR_DMI_ACPIBA 0x27B4 #define PCR_DMI_ACPIBDID 0x27B8 +#define PCR_DMI_DMICTL 0x2234 +#define PCR_DMI_DMICTL_SRLOCK (1 << 31) #define PCR_DMI_PMBASEA 0x27AC #define PCR_DMI_PMBASEC 0x27B0 19 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib340ff1ab7fd88b1e7b3860ffec055a75e562de7 Gerrit-Change-Number: 63472 Gerrit-PatchSet: 21 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/cmn/{block, pch}: Migrate GPMR driver
by Felix Held (Code Review) 20 Apr '22

20 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63471 ) Change subject: soc/intel/cmn/{block, pch}: Migrate GPMR driver ...................................................................... soc/intel/cmn/{block, pch}: Migrate GPMR driver This patch migrates GPMR driver over DMI to accommodate future SOCs with different interface (other than PCR/DMI). TEST=Able to build and boot google/redrix. Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I00ac667e8d3f2ccefd8d51a8150a989fc8e5c7e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63471 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/gpmr/gpmr.c M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/common/block/smbus/tco.c M src/soc/intel/common/pch/lockdown/lockdown.c 5 files changed, 23 insertions(+), 38 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 7e8a1a2..63fb68c 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -11,8 +11,8 @@ #include <commonlib/helpers.h> #include <cpu/x86/mtrr.h> #include <fast_spi_def.h> -#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/gpmr.h> #include <lib.h> #include <soc/pci_devs.h> #include <spi_flash.h> @@ -342,7 +342,7 @@ #endif /* Configure Source decode for Extended BIOS Region */ - if (dmi_enable_gpmr(CONFIG_EXT_BIOS_WIN_BASE, CONFIG_EXT_BIOS_WIN_SIZE, + if (enable_gpmr(CONFIG_EXT_BIOS_WIN_BASE, CONFIG_EXT_BIOS_WIN_SIZE, soc_get_spi_psf_destination_id()) == CB_ERR) return; diff --git a/src/soc/intel/common/block/gpmr/gpmr.c b/src/soc/intel/common/block/gpmr/gpmr.c index d0fe499..6c809a5 100644 --- a/src/soc/intel/common/block/gpmr/gpmr.c +++ b/src/soc/intel/common/block/gpmr/gpmr.c @@ -1,21 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> -#include <intelblocks/dmi.h> #include <intelblocks/gpmr.h> #include <intelblocks/pcr.h> #include <soc/pcr_ids.h> -#define MAX_GPMR_REGS 3 - -#define GPMR_OFFSET(x) (0x277c + (x) * 8) -#define DMI_PCR_GPMR_LIMIT_MASK 0xffff0000 -#define DMI_PCR_GPMR_BASE_SHIFT 16 -#define DMI_PCR_GPMR_BASE_MASK 0xffff - -#define GPMR_DID_OFFSET(x) (0x2780 + (x) * 8) -#define DMI_PCR_GPMR_EN BIT(31) - /* GPMR Register read given offset */ uint32_t gpmr_read32(uint16_t offset) { @@ -41,7 +30,7 @@ for (i = 0; i < MAX_GPMR_REGS; i++) { val = gpmr_read32(GPMR_DID_OFFSET(i)); - if (!(val & DMI_PCR_GPMR_EN)) + if (!(val & GPMR_EN)) return i; } printk(BIOS_ERR, "%s: No available free gpmr found\n", __func__); @@ -49,12 +38,12 @@ } /* Configure GPMR for the given base and size of extended BIOS Region */ -enum cb_err dmi_enable_gpmr(uint32_t base, uint32_t size, uint32_t dest_id) +enum cb_err enable_gpmr(uint32_t base, uint32_t size, uint32_t dest_id) { int gpmr_num; uint32_t limit; - if (base & ~(DMI_PCR_GPMR_BASE_MASK << DMI_PCR_GPMR_BASE_SHIFT)) { + if (base & ~(GPMR_BASE_MASK << GPMR_BASE_SHIFT)) { printk(BIOS_ERR, "base is not 64-KiB aligned!\n"); return CB_ERR; } @@ -66,7 +55,7 @@ return CB_ERR; } - if ((limit & ~DMI_PCR_GPMR_LIMIT_MASK) != 0xffff) { + if ((limit & ~GPMR_LIMIT_MASK) != 0xffff) { printk(BIOS_ERR, "limit does not end on a 64-KiB boundary!\n"); return CB_ERR; } @@ -77,11 +66,11 @@ return CB_ERR; /* Program Range for the given decode window */ - gpmr_write32(GPMR_OFFSET(gpmr_num), (limit & DMI_PCR_GPMR_LIMIT_MASK) | - ((base >> DMI_PCR_GPMR_BASE_SHIFT) & DMI_PCR_GPMR_BASE_MASK)); + gpmr_write32(GPMR_OFFSET(gpmr_num), (limit & GPMR_LIMIT_MASK) | + ((base >> GPMR_BASE_SHIFT) & GPMR_BASE_MASK)); /* Program source decode enable bit and the Destination ID */ - gpmr_write32(GPMR_DID_OFFSET(gpmr_num), dest_id | DMI_PCR_GPMR_EN); + gpmr_write32(GPMR_DID_OFFSET(gpmr_num), dest_id | GPMR_EN); return CB_SUCCESS; } diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index a44c2da..654dcea 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -7,6 +7,7 @@ #include <console/console.h> #include <device/pci.h> #include <device/pci_ops.h> +#include <intelblocks/gpmr.h> #include <intelblocks/itss.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> @@ -25,7 +26,7 @@ io_enables |= reg_io_enables; pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, io_enables); if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR)) - pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); + gpmr_write32(GPMR_LPCIOE, io_enables); return io_enables; } @@ -43,7 +44,7 @@ io_ranges |= reg_io_ranges & mask; pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, io_ranges); if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR)) - pcr_write16(PID_DMI, PCR_DMI_LPCIOD, io_ranges); + gpmr_write32(GPMR_LPCIOD, io_ranges); return io_ranges; } @@ -113,7 +114,7 @@ pci_write_config32(PCH_DEV_LPC, lgir_reg_offset, lgir); if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR)) - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1 + lgir_reg_num * 4, lgir); + gpmr_write32(GPMR_LPCLGIR1 + lgir_reg_num * 4, lgir); printk(BIOS_DEBUG, "LPC: Opened IO window LGIR%d: base %llx size %x\n", @@ -148,7 +149,7 @@ pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_MEM_RANGE, lgmr); if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR)) - pcr_write32(PID_DMI, PCR_DMI_LPCGMR, lgmr); + gpmr_write32(GPMR_LPCGMR, lgmr); } /* @@ -249,7 +250,7 @@ for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) { pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i), gen_io_dec[i]); if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR)) - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1 + i * 4, gen_io_dec[i]); + gpmr_write32(GPMR_LPCLGIR1 + i * 4, gen_io_dec[i]); } } diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c index 518541b..1ca8842 100644 --- a/src/soc/intel/common/block/smbus/tco.c +++ b/src/soc/intel/common/block/smbus/tco.c @@ -7,6 +7,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> +#include <intelblocks/gpmr.h> #include <intelblocks/pcr.h> #include <intelblocks/pmclib.h> #include <intelblocks/tco.h> @@ -16,10 +17,6 @@ #include <soc/pm.h> #include <soc/smbus.h> -#define PCR_DMI_TCOBASE 0x2778 -/* Enable TCO I/O range decode. */ -#define TCOEN (1 << 1) - /* SMBUS TCO base address. */ #define TCOBASE 0x50 #define TCOCTL 0x54 @@ -122,10 +119,8 @@ /* Enable TCO in SMBUS */ pci_write_config32(dev, TCOCTL, reg32 | TCO_BASE_EN); - /* - * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] - */ - pcr_write32(PID_DMI, PCR_DMI_TCOBASE, tcobase | TCOEN); + /* Program TCO Base Address */ + gpmr_write32(GPMR_TCOBASE, tcobase | GPMR_TCOEN); } /* diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index 5ab0611..739d135 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -2,10 +2,10 @@ #include <bootstate.h> #include <intelblocks/cfg.h> -#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/pcr.h> #include <intelpch/lockdown.h> +#include <intelblocks/gpmr.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> #include <soc/soc_chip.h> @@ -25,7 +25,7 @@ return common_config->chipset_lockdown; } -static void dmi_lockdown_cfg(void) +static void lockdown_cfg(void) { /* * GCS reg of DMI @@ -37,13 +37,13 @@ * "0b": SPI * "1b": LPC/eSPI */ - pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD); + gpmr_or32(GPMR_GCS, GPMR_GCS_BILD); /* * Set Secure Register Lock (SRL) bit in DMI control register to lock * DMI configuration. */ - pcr_or32(PID_DMI, PCR_DMI_DMICTL, PCR_DMI_DMICTL_SRLOCK); + gpmr_or32(GPMR_DMICTL, GPMR_DMICTL_SRLOCK); } static void fast_spi_lockdown_cfg(int chipset_lockdown) @@ -94,7 +94,7 @@ fast_spi_lockdown_cfg(chipset_lockdown); /* DMI lock down configuration */ - dmi_lockdown_cfg(); + lockdown_cfg(); /* SoC lock down configuration */ soc_lockdown_config(chipset_lockdown); 13 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00ac667e8d3f2ccefd8d51a8150a989fc8e5c7e2 Gerrit-Change-Number: 63471 Gerrit-PatchSet: 15 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/redrix: Add alias back to RP6 WWAN device
by Felix Held (Code Review) 20 Apr '22

20 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63556 ) Change subject: mb/google/brya/var/redrix: Add alias back to RP6 WWAN device ...................................................................... mb/google/brya/var/redrix: Add alias back to RP6 WWAN device This alias name is required for the mainboard.c code to generate the appropriate power-off seqeuence for use during orderly S5 shutdown from the OS. It had been accidentally removed, but is required, so this patch adds it. BUG=b:227788351 TEST=compile Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I8936a01bd3a6b908033a8c58bd4e84b30d199e98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63556 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/variants/redrix/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index 149b4f3..8ea8769 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -198,7 +198,7 @@ register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)" register "add_acpi_dma_property" = "true" use rp6_rtd3 as rtd3dev - device generic 0 on + device generic 0 alias rp6_wwan on probe DB_LTE LTE_PCIE end end -- To view, visit https://review.coreboot.org/c/coreboot/+/63556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8936a01bd3a6b908033a8c58bd4e84b30d199e98 Gerrit-Change-Number: 63556 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp_n: Disable SATA controller
by Felix Held (Code Review) 20 Apr '22

20 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63443 ) Change subject: mb/intel/adlrvp_n: Disable SATA controller ...................................................................... mb/intel/adlrvp_n: Disable SATA controller Disable SATA config from devicetree for ADL-N RVP, since we are not planning to use it in chrome config. Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: Ic9dce3a0b06e1a0d0d9fa495aa406eb12557d842 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63443 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> --- M src/mainboard/intel/adlrvp/devicetree_n.cb 1 file changed, 2 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Kangheui Won: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb index 2b7eca6..57a3701 100644 --- a/src/mainboard/intel/adlrvp/devicetree_n.cb +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -54,21 +54,7 @@ .flags = PCIE_RP_CLK_REQ_DETECT, }" - register "sata_salp_support" = "1" - - register "sata_ports_enable" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - [3] = 1, - }" - - register "sata_ports_dev_slp" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - [3] = 1, - }" + register "sata_salp_support" = "0" # Enable EDP in PortA register "ddi_portA_config" = "1" @@ -241,7 +227,7 @@ device ref i2c2 on end device ref i2c3 on end device ref heci1 on end - device ref sata on end + device ref sata off end device ref i2c5 on chip drivers/intel/mipi_camera register "acpi_hid" = ""OVTI5675"" -- To view, visit https://review.coreboot.org/c/coreboot/+/63443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9dce3a0b06e1a0d0d9fa495aa406eb12557d842 Gerrit-Change-Number: 63443 Gerrit-PatchSet: 2 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/snb: Reduce scope of functions
by Felix Held (Code Review) 20 Apr '22

20 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63701 ) Change subject: nb/intel/snb: Reduce scope of functions ...................................................................... nb/intel/snb: Reduce scope of functions Change-Id: Idefbe15c5f7c7169d9b60079b90cd02affb261ca Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63701 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit.h M src/northbridge/intel/sandybridge/raminit_mrc.c 2 files changed, 5 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Felix Singer: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/sandybridge/raminit.h b/src/northbridge/intel/sandybridge/raminit.h index dd4e572..fa9fa98 100644 --- a/src/northbridge/intel/sandybridge/raminit.h +++ b/src/northbridge/intel/sandybridge/raminit.h @@ -9,10 +9,6 @@ #define BOOT_PATH_RESET 1 #define BOOT_PATH_RESUME 2 -void sdram_initialize(struct pei_data *pei_data); -void save_mrc_data(struct pei_data *pei_data); void mainboard_fill_pei_data(struct pei_data *pei_data); -int fixup_sandybridge_errata(void); -void setup_sdram_meminfo(struct pei_data *pei_data); #endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index fbb2b6e..0bc33b6 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -49,7 +49,7 @@ #define MRC_CACHE_VERSION 0 -void save_mrc_data(struct pei_data *pei_data) +static void save_mrc_data(struct pei_data *pei_data) { u16 c1, c2, checksum; @@ -127,7 +127,7 @@ * * @param pei_data: configuration data for UEFI PEI reference code */ -void sdram_initialize(struct pei_data *pei_data) +static void sdram_initialize(struct pei_data *pei_data) { int (*entry)(struct pei_data *pei_data) __attribute__((regparm(1))); @@ -320,6 +320,8 @@ RCBA32(FD) |= PCH_DISABLE_P2P; } +static void setup_sdram_meminfo(struct pei_data *pei_data); + void perform_raminit(int s3resume) { struct pei_data pei_data; @@ -390,7 +392,7 @@ setup_sdram_meminfo(&pei_data); } -void setup_sdram_meminfo(struct pei_data *pei_data) +static void setup_sdram_meminfo(struct pei_data *pei_data) { u32 addr_decoder_common, addr_decode_ch[2]; struct memory_info *mem_info; -- To view, visit https://review.coreboot.org/c/coreboot/+/63701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idefbe15c5f7c7169d9b60079b90cd02affb261ca Gerrit-Change-Number: 63701 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/anahera{4es}: Enable power saving for Smart Card
by Felix Held (Code Review) 20 Apr '22

20 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63648 ) Change subject: mb/google/brya/var/anahera{4es}: Enable power saving for Smart Card ...................................................................... mb/google/brya/var/anahera{4es}: Enable power saving for Smart Card Configure the power saving pin for Smart Card. BUG=b:229356121 TEST=emerge-brya coreboot chromeos-bootimage Change-Id: Ia17970f717c6ba806d9603031c486bad86e42b37 Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63648 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/anahera/gpio.c M src/mainboard/google/brya/variants/anahera4es/gpio.c 2 files changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/anahera/gpio.c b/src/mainboard/google/brya/variants/anahera/gpio.c index 9483d56..02ebeb8 100644 --- a/src/mainboard/google/brya/variants/anahera/gpio.c +++ b/src/mainboard/google/brya/variants/anahera/gpio.c @@ -61,6 +61,8 @@ PAD_CFG_GPO(GPP_E16, 1, DEEP), /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ PAD_CFG_GPO(GPP_E20, 1, DEEP), + /* E22 : DDPA_CTRLCLK ==> SC_PWR_SV */ + PAD_CFG_GPO(GPP_E22, 1, DEEP), /* E23 : DDPA_CTRLDATA ==> NC */ PAD_NC(GPP_E23, NONE), diff --git a/src/mainboard/google/brya/variants/anahera4es/gpio.c b/src/mainboard/google/brya/variants/anahera4es/gpio.c index 132dbf6..12f73fc 100644 --- a/src/mainboard/google/brya/variants/anahera4es/gpio.c +++ b/src/mainboard/google/brya/variants/anahera4es/gpio.c @@ -65,6 +65,8 @@ PAD_CFG_GPO(GPP_E16, 1, DEEP), /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ PAD_CFG_GPO(GPP_E20, 1, DEEP), + /* E22 : DDPA_CTRLCLK ==> SC_PWR_SV */ + PAD_CFG_GPO(GPP_E22, 1, DEEP), /* E23 : DDPA_CTRLDATA ==> NC */ PAD_NC(GPP_E23, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/63648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia17970f717c6ba806d9603031c486bad86e42b37 Gerrit-Change-Number: 63648 Gerrit-PatchSet: 2 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush/var/dewatt: Override SPI fast speed
by Felix Held (Code Review) 20 Apr '22

20 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63685 ) Change subject: mb/google/guybrush/var/dewatt: Override SPI fast speed ...................................................................... mb/google/guybrush/var/dewatt: Override SPI fast speed After assessing the signal integrity, 100 MHz SPI fast speed can be enabled for SPI ROM. BUG=b:213403891 TEST=Build and boot to OS in Dewatt board version 2. Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Change-Id: I7301d873e36bec4ee46c9d18293f924500ea9aba Reviewed-on: https://review.coreboot.org/c/coreboot/+/63685 Reviewed-by: Rob Barnes <robbarnes(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/guybrush/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Kenneth Chan: Looks good to me, but someone else must approve Rob Barnes: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index b2cba6e..069da6c 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -140,7 +140,7 @@ config OVERRIDE_EFS_SPI_SPEED_MIN_BOARD hex default 0x4 if BOARD_GOOGLE_GUYBRUSH - default 0x2 if BOARD_GOOGLE_NIPPERKIN + default 0x2 if BOARD_GOOGLE_NIPPERKIN || BOARD_GOOGLE_DEWATT default 0xffffffff help Minimum board version starting which the Override EFS SPI Speed -- To view, visit https://review.coreboot.org/c/coreboot/+/63685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7301d873e36bec4ee46c9d18293f924500ea9aba Gerrit-Change-Number: 63685 Gerrit-PatchSet: 2 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/picasso: Use read*p
by Arthur Heymans (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Angel Pons, Fred Reitberger, Felix Held. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63726 ) Change subject: soc/amd/picasso: Use read*p ...................................................................... Patch Set 3: (1 comment) File src/soc/amd/common/block/cpu/smm/smi_apmc_helper.c: https://review.coreboot.org/c/coreboot/+/63726/comment/df8e8e6b_b8d84241 PS3, Line 85: size_t > Why not `uintptr_t`? It should be as it's really used as a pointer. -- To view, visit https://review.coreboot.org/c/coreboot/+/63726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29fdb73ae1c0508796a21b650bf4fd1ac6688021 Gerrit-Change-Number: 63726 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 20 Apr 2022 09:15:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taniks: Add WiFi SAR table for taniks
by Leo Chou (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Jerry2 Huang, Kevin Chang, Joey Peng, Tim Wawrzynczak, YH Lin, Sunshine Chao. Leo Chou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63684 ) Change subject: mb/google/brya/var/taniks: Add WiFi SAR table for taniks ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/63684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b52f71b1fe49c02beaa48410495b81661b58fac Gerrit-Change-Number: 63684 Gerrit-PatchSet: 2 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Attention: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Wed, 20 Apr 2022 08:51:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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