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Change subject: soc/intel/alderlake: Implement PMC feature lock
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/alderlake/lockdown.c:
https://review.coreboot.org/c/coreboot/+/63691/comment/132583d2_60d7f60d
PS4, Line 28: setbits32(pmc_mmio_regs() + PM_CFG, PM_CFG_DBG_MODE_LOCK |
Will add more settings? Maybe create a structure to maintain it? If just 3, it's fine.
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Change subject: soc/intel/alderlake: Implement PMC feature lock
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Patch Set 4: Code-Review+2
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Change subject: soc/intel/alderlake: Implement PMC soft strap interface lock
......................................................................
Patch Set 4: Code-Review+2
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Change subject: soc/intel/alderlake: Implement PMC static function lock
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Patch Set 3: Code-Review+2
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Change subject: intel/common/../systemagent: Add sa_get_mchbar_base api
......................................................................
Patch Set 7:
(3 comments)
File src/soc/intel/common/block/systemagent/systemagent_early.c:
https://review.coreboot.org/c/coreboot/+/63615/comment/b6b237a9_86f8bcf3
PS7, Line 89: if(mchbar_lo & 0x1)
one space between `if` and `(`
https://review.coreboot.org/c/coreboot/+/63615/comment/c2a51e1d_1020e8c4
PS7, Line 91:
same
https://review.coreboot.org/c/coreboot/+/63615/comment/ec4b1786_6798d7d2
PS7, Line 91:
remove space
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Change subject: soc/intel/alderlake: Implement PMC static function lock
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/alderlake/lockdown.c:
https://review.coreboot.org/c/coreboot/+/63689/comment/3877b5b6_c5573ec5
PS2, Line 60: /* PMSYNC */
: pmc_lock_pmsync();
: /* Lock down ABASE and sleep stretching policy */
: pmc_lock_abase();
:
: if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT)
: pmc_lock_smi();
:
: if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM))
: pmc_st_pg_lock();
> Noting that this file is basically just setting a few bits in some PMBASE registers, do we need another function to get pmcbase, etc. ? seems like this whole file could be more like 10 lines long?
>
> ```
> static void pmc_lockdown_cfg(int chipset_lockdown)
> {
> setbits32(pmc_mmio_regs() + PMSYNC_TPR_CFG, PCH2CPU_TPR_CFG_LOCK);
> setbits32(pmc_mmio_regs() + GEN_PMCON_B, SLPSTR_PL_LOCK | ACPI_BASE_LOCK);
> if (chipset_lockdown)
> setbits8(pmc_mmio_regs() + GEN_PMCON_B, SMI_LOCK);
> if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM))
> setbits32(pmc_mmio_regs() + ST_PG_FDIS1, ST_FDIS_LOCK);
> }
>
> void soc_lockdown_config(int chipset_lockdown)
> {
> pmc_lockdown_cfg(chipset_lockdown);
> }
> ```
done, CB:63737 does the refactoring prior to adding new changes.
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Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Eric Lai, Lean Sheng Tan, Werner Zeh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63692
to look at the new patch set (#4).
Change subject: soc/intel/alderlake: Implement PCH lock down configuration
......................................................................
soc/intel/alderlake: Implement PCH lock down configuration
This patch implements a function to enable IOSF Primary Trunk Clock
Gating.
BUG=b:211954778
TEST=Able to build and boot google/redrix to OS.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ie28dde8f62adc5bafc4a42e608827f51da82570c
---
M src/soc/intel/alderlake/lockdown.c
1 file changed, 17 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/63692/4
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