coreboot-gerrit April 2022

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Change in coreboot[master]: mb/google/brya/var/crota: Limit dram speed to 4800 MT/s
by Scott Chao (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Eric Lai. Hello build bot (Jenkins), Paul Menzel, Tim Wawrzynczak, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63682 to look at the new patch set (#7). Change subject: mb/google/brya/var/crota: Limit dram speed to 4800 MT/s ...................................................................... mb/google/brya/var/crota: Limit dram speed to 4800 MT/s When using LPDDR5 on a Type-C PCB, the Intel ADL-P PDG(Rev. 2.0.1) Chapter 4.10 recommends a maximum DRAM speed of 4800 MT/s. BUG=b:229549930 BRANCH=none TEST=build and pass memory training Signed-off-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Change-Id: I38f0006d478702afb382d30338f20b46641964ef --- M src/mainboard/google/brya/variants/crota/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/63682/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/63682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38f0006d478702afb382d30338f20b46641964ef Gerrit-Change-Number: 63682 Gerrit-PatchSet: 7 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib: Check for non-existent DIMMs in check_if_dimm_changed
by Subrata Banik (Code Review) 20 Apr '22

20 Apr '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63628 ) Change subject: lib: Check for non-existent DIMMs in check_if_dimm_changed ...................................................................... lib: Check for non-existent DIMMs in check_if_dimm_changed Treat dimm addr_map 0 non-existent. addr_map default is 0, we don't set it if Hw is not present. Also change the test case default to avoid 0. SODIMM SMbus address 0x50 to 0x53 is commonly used. BUG=b:213964936 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage The MRC training does not be performed again after rebooting. Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: I2ada0109eb0805174cb85d4ce373e2a3ab7dbcac Reviewed-on: https://review.coreboot.org/c/coreboot/+/63628 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/lib/spd_cache.c M tests/lib/spd_cache-test.c 2 files changed, 14 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Frank Wu: Looks good to me, approved Lean Sheng Tan: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/lib/spd_cache.c b/src/lib/spd_cache.c index 44830a8..dff6ede 100644 --- a/src/lib/spd_cache.c +++ b/src/lib/spd_cache.c @@ -155,6 +155,10 @@ bool dimm_changed = false; /* Check if the dimm is the same with last system boot. */ for (i = 0; i < SC_SPD_NUMS && !dimm_changed; i++) { + if (blk->addr_map[i] == 0) { + printk(BIOS_NOTICE, "SPD_CACHE: DIMM%d does not exist\n", i); + continue; + } /* Return true if any error happened here. */ if (get_spd_sn(blk->addr_map[i], &sn) == CB_ERR) return true; diff --git a/tests/lib/spd_cache-test.c b/tests/lib/spd_cache-test.c index e1c1777..48f06e3 100644 --- a/tests/lib/spd_cache-test.c +++ b/tests/lib/spd_cache-test.c @@ -146,7 +146,8 @@ { uint8_t *spd_cache; size_t spd_cache_sz; - struct spd_block blk = {.addr_map = {0}, .spd_array = {0}, .len = 0}; + struct spd_block blk = {.addr_map = {0x50, 0x51, 0x52, 0x53}, + .spd_array = {0}, .len = 0}; assert_int_equal(CB_SUCCESS, load_spd_cache(&spd_cache, &spd_cache_sz)); fill_spd_cache_ddr4(spd_cache, spd_cache_sz); @@ -162,7 +163,8 @@ { uint8_t *spd_cache; size_t spd_cache_sz; - struct spd_block blk = {.addr_map = {0}, .spd_array = {0}, .len = 0}; + struct spd_block blk = {.addr_map = {0x50, 0x51, 0x52, 0x53}, + .spd_array = {0}, .len = 0}; assert_int_equal(CB_SUCCESS, load_spd_cache(&spd_cache, &spd_cache_sz)); fill_spd_cache_ddr4(spd_cache, spd_cache_sz); @@ -177,7 +179,8 @@ { uint8_t *spd_cache; size_t spd_cache_sz; - struct spd_block blk = {.addr_map = {0}, .spd_array = {0}, .len = 0}; + struct spd_block blk = {.addr_map = {0x50, 0x51, 0x52, 0x53}, + .spd_array = {0}, .len = 0}; assert_int_equal(CB_SUCCESS, load_spd_cache(&spd_cache, &spd_cache_sz)); fill_spd_cache_ddr4(spd_cache, spd_cache_sz); @@ -194,7 +197,8 @@ { uint8_t *spd_cache; size_t spd_cache_sz; - struct spd_block blk = {.addr_map = {0}, .spd_array = {0}, .len = 0}; + struct spd_block blk = {.addr_map = {0x50, 0x51, 0x52, 0x53}, + .spd_array = {0}, .len = 0}; assert_int_equal(CB_SUCCESS, load_spd_cache(&spd_cache, &spd_cache_sz)); fill_spd_cache_ddr4(spd_cache, spd_cache_sz); @@ -212,7 +216,8 @@ { uint8_t *spd_cache; size_t spd_cache_sz; - struct spd_block blk = {.addr_map = {0}, .spd_array = {0}, .len = 0}; + struct spd_block blk = {.addr_map = {0x50, 0x51, 0x52, 0x53}, + .spd_array = {0}, .len = 0}; assert_int_equal(CB_SUCCESS, load_spd_cache(&spd_cache, &spd_cache_sz)); fill_spd_cache_ddr4(spd_cache, spd_cache_sz); -- To view, visit https://review.coreboot.org/c/coreboot/+/63628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ada0109eb0805174cb85d4ce373e2a3ab7dbcac Gerrit-Change-Number: 63628 Gerrit-PatchSet: 11 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: lib: Check for non-existent DIMMs in check_if_dimm_changed
by Subrata Banik (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Jakub Czapiga, Ivy Jian, Eric Lai, Felix Held. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63628 ) Change subject: lib: Check for non-existent DIMMs in check_if_dimm_changed ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ada0109eb0805174cb85d4ce373e2a3ab7dbcac Gerrit-Change-Number: 63628 Gerrit-PatchSet: 10 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 20 Apr 2022 06:57:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/crota: Limit dram speed to 4800 MT/s
by Scott Chao (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Scott Chao, Eric Lai. Hello build bot (Jenkins), Paul Menzel, Tim Wawrzynczak, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63682 to look at the new patch set (#6). Change subject: mb/google/brya/var/crota: Limit dram speed to 4800 MT/s ...................................................................... mb/google/brya/var/crota: Limit dram speed to 4800 MT/s When using LPDDR5 on a Type-C PCB, the Intel PDG recommends a maximum DRAM speed of 4800 MT/s. BUG=b:229549930 BRANCH=none TEST=build and pass memory training Signed-off-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Change-Id: I38f0006d478702afb382d30338f20b46641964ef --- M src/mainboard/google/brya/variants/crota/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/63682/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/63682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38f0006d478702afb382d30338f20b46641964ef Gerrit-Change-Number: 63682 Gerrit-PatchSet: 6 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/smbus: Add `finalize` operation for smbus
by Subrata Banik (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Felix Singer, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Lean Sheng Tan, Eric Lai, Werner Zeh. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63640 ) Change subject: soc/intel/common/smbus: Add `finalize` operation for smbus ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/common/block/smbus/smbus.c: https://review.coreboot.org/c/coreboot/+/63640/comment/1de50379_a854c0bb PS5, Line 77: tco_lockdown(); > So why is this call even necessary here, because it is already taken care of in pch_finalize regardless? Seems like this part (of FSP PCI enum finalize step) is already taken care of in current coreboot code. In case we have SMBUS PCI device is visible over PCI Bus, it's important to ensure that TCO base address is locked before running 3rd party code (like Option ROM), hence, Intel security guideline recommended to lock TCO base with FSP Notify Phase 1 API call(on PCI enumeration). -- To view, visit https://review.coreboot.org/c/coreboot/+/63640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie945680049514e6c5d797790a381a6946e836926 Gerrit-Change-Number: 63640 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Wed, 20 Apr 2022 06:40:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/{sa, adl}: Add `finalize` operation for systemagent
by Subrata Banik (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Arthur Heymans. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63518 ) Change subject: soc/intel/common/{sa, adl}: Add `finalize` operation for systemagent ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/common/block/systemagent/systemagent.c: https://review.coreboot.org/c/coreboot/+/63518/comment/a074f0e4_90a7d1ae PS7, Line 327: if (!CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE)) : sa_lock_pam(); > What about the lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT on line 79? Shouldn't this code take that into account as well? There potentially could be three cases as below: 1. SoC user decides to call FSP Notify Phase API but like to keep `common_config->chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT` 2. The SoC user decides to call FSP Notify Phase API and to keep `common_config->chipset_lockdown = CHIPSET_LOCKDOWN_FSP` 3. SoC user decides to skip FSP Notify Phase API For #1:soc/intel/alderlake/finalize.c function sa_finalize will perform the PAM register lock. For #2:FSP takes care of locking using FSP notify phase 2 API For #3:This code change src/soc/intel/common/block/systemagent/systemagent.c#325 ensures to lockdown PAM registers using common code, so, we don't need to implement the SoC specific implementation going forward for MTL for example. Also, PAM register attribute is RW/L, once programmed by IA common code as part of `.final` callback, SoC specific implementation doesn't have any significance. -- To view, visit https://review.coreboot.org/c/coreboot/+/63518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd464d2507393ed0c746eb1fbd10e36092ed5599 Gerrit-Change-Number: 63518 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 20 Apr 2022 06:37:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec: allow custom command timeout
by Paul Menzel (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Tim Wawrzynczak, Peter Marheine. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63733 ) Change subject: ec/google/chromeec: allow custom command timeout ...................................................................... Patch Set 1: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63733/comment/cc2ea0ac_fd6e5c1a PS1, Line 15: timeout field is zero-initialized when the default should be used Why can’t it be initialized to 1 s explicitly? Having 0 mean different things, is not nice in my opinion. https://review.coreboot.org/c/coreboot/+/63733/comment/e6584633_20b74db0 PS1, Line 17: When is EC flash erase done, that means, when will the user experience that? Should some message logged, when it is taking longer than a few milliseconds (separate commit)? File src/ec/google/chromeec/ec.h: https://review.coreboot.org/c/coreboot/+/63733/comment/3c06ab71_4088af35 PS1, Line 157: uint32_t timeout_us; /* maximum time to wait for command completion Why not use a native type? -- To view, visit https://review.coreboot.org/c/coreboot/+/63733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55d36479e680c34a8bff65776e7e295e94291342 Gerrit-Change-Number: 63733 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Wed, 20 Apr 2022 06:35:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Fix accessing Descriptor Region access
by Sridhar Siricilla (Code Review) 20 Apr '22

20 Apr '22

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63734 ) Change subject: soc/intel/common: Fix accessing Descriptor Region access ...................................................................... soc/intel/common: Fix accessing Descriptor Region access The patch fixes the buggy code which tries to access the Descriptor Region. TEST=Build and verify no errors seen while accessing the Descriptor Region. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ib144cc0845b7527e5a3032529b0802f961944b87 --- M src/soc/intel/common/basecode/debug/debug_feature.c 1 file changed, 3 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/63734/1 diff --git a/src/soc/intel/common/basecode/debug/debug_feature.c b/src/soc/intel/common/basecode/debug/debug_feature.c index 5cdbaf7..ed6974e 100644 --- a/src/soc/intel/common/basecode/debug/debug_feature.c +++ b/src/soc/intel/common/basecode/debug/debug_feature.c @@ -6,6 +6,7 @@ #include <console/console.h> #include <fmap.h> +#define CONFIG_SI_DESC_REGION "SI_DESC" #define SI_DESC_OEM_SECTION_OFFSET 0xF00 #define PRE_MEM_FEATURE_CTRL_OFFSET SI_DESC_OEM_SECTION_OFFSET #define PRE_MEM_FEATURE_CTRL_SZ 64 @@ -23,15 +24,9 @@ uint8_t pre_mem_debug_init(void) { struct region_device desc_rdev; - const struct region_device *boot_device = boot_device_ro(); - if (!boot_device) { - printk(BIOS_ERR, "Failed to get RW boot device\n"); - return 1; - } - - if (rdev_chain(&desc_rdev, boot_device, 0, SI_DESC_REGION_SZ)) { - printk(BIOS_ERR, "Failed to get description region device\n"); + if (fmap_locate_area_as_rdev_rw(CONFIG_SI_DESC_REGION, &desc_rdev) < 0) { + printk(BIOS_ERR, "Failed to locate %s in the FMAP\n", CONFIG_SI_DESC_REGION); return 1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/63734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib144cc0845b7527e5a3032529b0802f961944b87 Gerrit-Change-Number: 63734 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Add support to control CSE firmware update
by Sridhar Siricilla (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Rizwan Qureshi, Sridhar Siricilla, Arthur Heymans, Patrick Rudolph. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62715 to look at the new patch set (#5). Change subject: soc/intel/common: Add support to control CSE firmware update ...................................................................... soc/intel/common: Add support to control CSE firmware update The patch adds support to control CSE Lite firmware update dynamically. In order to disable the CSE firmware update functionality, offset 0xf00 in the coreboot binary be updated with 0x1. Run below command on the binary to disable CSE firmwar update printf '\x01' | dd of=image-brya4es.serial.bin bs=1 seek=3840 count=1 conv=notrunc BUG=b:153410586 TEST=Verified CSE firmware update functionality is not getting triggered after updating the offset:0xF00 in the coreboot binary. ........................ CB Logs ...................................... [DEBUG] prev_sleep_state 5 [DEBUG] cse_lite: Number of partitions = 3 [DEBUG] cse_lite: Current partition = RW [DEBUG] cse_lite: Next partition = RW [DEBUG] cse_lite: Flags = 0x3 [DEBUG] cse_lite: RO version = 16.0.15.1752 (Status=0x0, Start=0x2000, End=0x19bfff) [DEBUG] cse_lite: RW version = 16.0.15.1752 (Status=0x0, Start=0x205000, End=0x439fff) rt_debug: pre_mem_debug.cse_fw_update_disable=1 [DEBUG] Boot Count incremented to 956 ....................................................................... Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I9f234b142191eb83137d5d83f21e890e1cb828ba --- M src/soc/intel/common/basecode/debug/debug_feature.c M src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h M src/soc/intel/common/block/cse/cse_lite.c 3 files changed, 30 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/62715/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/62715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f234b142191eb83137d5d83f21e890e1cb828ba Gerrit-Change-Number: 62715 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/brya0: configure gpio for headset
by Frank Wu (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Tim Wawrzynczak, Amanda Hwang, Felix Held. Frank Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63721 ) Change subject: mb/google/brya/var/brya0: configure gpio for headset ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93070a8096d43557a50e5a545227f2906e299d8e Gerrit-Change-Number: 63721 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 20 Apr 2022 06:28:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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