coreboot-gerrit April 2022

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Change in coreboot[master]: soc/intel/alderlake: Add _DSM method for CNVi WiFi
by Ronak Kanabar (Code Review) 20 Apr '22

20 Apr '22

Ronak Kanabar has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/58324 ) Change subject: soc/intel/alderlake: Add _DSM method for CNVi WiFi ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/58324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebb234d4e2e3f60d65fa76d41db4c7eea6324437 Gerrit-Change-Number: 58324 Gerrit-PatchSet: 9 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/jasperlake: CNVi: Enable fewer wakeups to reduce SoC power ...
by Paul Menzel (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Jamie Chen, Tim Wawrzynczak, Karthik Ramasubramanian. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63675 ) Change subject: soc/intel/jasperlake: CNVi: Enable fewer wakeups to reduce SoC power consumption ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56439a406547e2ee1e47d34be14ecc9a8df04693 Gerrit-Change-Number: 63675 Gerrit-PatchSet: 5 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 20 Apr 2022 06:18:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: CNVi: Enable fewer wakeups to reduce SoC power ...
by Jamie Chen (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Karthik Ramasubramanian. Jamie Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63675 ) Change subject: soc/intel/jasperlake: CNVi: Enable fewer wakeups to reduce SoC power consumption ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63675/comment/4ea5fc54_eb50a9ca PS3, Line 7: soc/intel/jasperlake: Add a workaround for cnvi > Yes, the prefix should be kept. Please add CNVi after the prefix though. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56439a406547e2ee1e47d34be14ecc9a8df04693 Gerrit-Change-Number: 63675 Gerrit-PatchSet: 5 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 20 Apr 2022 06:08:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jamie Chen <jamie.chen(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: CNVi: Enable fewer wakeups to reduce SoC power ...
by Jamie Chen (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Jamie Chen, Tim Wawrzynczak, Karthik Ramasubramanian. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Tim Wawrzynczak, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63675 to look at the new patch set (#5). Change subject: soc/intel/jasperlake: CNVi: Enable fewer wakeups to reduce SoC power consumption ...................................................................... soc/intel/jasperlake: CNVi: Enable fewer wakeups to reduce SoC power consumption According to Intel TA#724456, work around the higher SoC power consumption in S0iX when CNVI has background activity. BUG=b:201263040 TEST=Turn on this setting and build and verify on Drawcia. The SLP_S0 toggling become slower or gone at the same CNVI background activity. Change-Id: I56439a406547e2ee1e47d34be14ecc9a8df04693 Signed-off-by: Jamie Chen <jamie.chen(a)intel.com> --- M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/finalize.c M src/soc/intel/jasperlake/include/soc/pmc.h 3 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/63675/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/63675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56439a406547e2ee1e47d34be14ecc9a8df04693 Gerrit-Change-Number: 63675 Gerrit-PatchSet: 5 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/jasperlake: Enable fewer wakeups to reduce SoC power consum...
by Paul Menzel (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Jamie Chen, Tim Wawrzynczak, Karthik Ramasubramanian. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63675 ) Change subject: soc/intel/jasperlake: Enable fewer wakeups to reduce SoC power consumption ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63675/comment/6a4c686a_ebe7b2ff PS3, Line 7: soc/intel/jasperlake: Add a workaround for cnvi > keep the prefix because this is for JSL only. Yes, the prefix should be kept. Please add CNVi after the prefix though. -- To view, visit https://review.coreboot.org/c/coreboot/+/63675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56439a406547e2ee1e47d34be14ecc9a8df04693 Gerrit-Change-Number: 63675 Gerrit-PatchSet: 4 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 20 Apr 2022 06:03:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jamie Chen <jamie.chen(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Enable fewer wakeups to reduce SoC power consum...
by Subrata Banik (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Jamie Chen, Paul Menzel, Tim Wawrzynczak, Karthik Ramasubramanian. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63675 ) Change subject: soc/intel/jasperlake: Enable fewer wakeups to reduce SoC power consumption ...................................................................... Patch Set 4: Code-Review+1 (1 comment) Patchset: PS4: LGTM -- To view, visit https://review.coreboot.org/c/coreboot/+/63675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56439a406547e2ee1e47d34be14ecc9a8df04693 Gerrit-Change-Number: 63675 Gerrit-PatchSet: 4 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 20 Apr 2022 05:55:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/cse: Simplify CSE final ops
by Eric Lai (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Arthur Heymans. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63708 ) Change subject: soc/intel/common/block/cse: Simplify CSE final ops ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65fcb2fc02ea16b37c764f1fd69bdff3382fad18 Gerrit-Change-Number: 63708 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 20 Apr 2022 05:51:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec: allow custom command timeout
by Eric Lai (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Tim Wawrzynczak, Peter Marheine. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63733 ) Change subject: ec/google/chromeec: allow custom command timeout ...................................................................... Patch Set 1: (2 comments) File src/ec/google/chromeec/ec_lpc.c: https://review.coreboot.org/c/coreboot/+/63733/comment/f790da94_552d6e9c PS1, Line 236: printk(BIOS_ERR, "Timeout waiting for EC process command %d!\n", Maybe add timeout_us in log? https://review.coreboot.org/c/coreboot/+/63733/comment/39350da4_2937838e PS1, Line 313: printk(BIOS_ERR, "Timeout waiting for EC process command %d!\n", Maybe add timeout_us in log? -- To view, visit https://review.coreboot.org/c/coreboot/+/63733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55d36479e680c34a8bff65776e7e295e94291342 Gerrit-Change-Number: 63733 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Wed, 20 Apr 2022 05:49:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Set half_populated true for ADL-N
by Rizwan Qureshi (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: V Sowmya, Paul Menzel, Arthur Heymans, Balaji Manigandan, Krishna P Bhat D, Usha P. Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62913 ) Change subject: mb/intel/adlrvp: Set half_populated true for ADL-N ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ecc3018a1ab039990ba47898ff0e0e2ede695cc Gerrit-Change-Number: 62913 Gerrit-PatchSet: 14 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Kangheui Won <khwon(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Wed, 20 Apr 2022 05:45:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec: allow custom command timeout
by Peter Marheine (Code Review) 20 Apr '22

20 Apr '22

Peter Marheine has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63733 ) Change subject: ec/google/chromeec: allow custom command timeout ...................................................................... ec/google/chromeec: allow custom command timeout EC flash erase commands can take longer than a second to complete on some devices (nearly five seconds was observed on Nereid). Allow commands to specify a custom timeout, and retain the current one second timeout if unspecified. Several google_chromeec_command() callers are modified to ensure the timeout field is zero-initialized when the default should be used, and google_chromeec_flash_erase() has its timeout set to 10 seconds. BUG=b:222987250 TEST=EC flash erase no longer times out on Nereid Signed-off-by: Peter Marheine <pmarheine(a)chromium.org> Change-Id: I55d36479e680c34a8bff65776e7e295e94291342 --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h M src/ec/google/chromeec/ec_lpc.c 3 files changed, 41 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/63733/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 5d53926..eaeeaa2 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -598,6 +598,8 @@ .cmd_size_out = 0, .cmd_data_out = NULL, .cmd_dev_index = 0, + /* Some ECs are known to need multiple seconds to erase */ + .timeout_us = 10 * USECS_PER_SEC, }; if (google_chromeec_command(&cmd) != 0) @@ -608,15 +610,15 @@ int google_chromeec_flash_info(struct ec_response_flash_info *info) { - struct chromeec_command cmd; - - cmd.cmd_code = EC_CMD_FLASH_INFO; - cmd.cmd_version = 0; - cmd.cmd_size_in = 0; - cmd.cmd_data_in = NULL; - cmd.cmd_size_out = sizeof(*info); - cmd.cmd_data_out = info; - cmd.cmd_dev_index = 0; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_FLASH_INFO, + .cmd_version = 0, + .cmd_size_in = 0, + .cmd_data_in = NULL, + .cmd_size_out = sizeof(*info), + .cmd_data_out = info, + .cmd_dev_index = 0, + }; if (google_chromeec_command(&cmd) != 0) return -1; @@ -1087,13 +1089,15 @@ msg->len = read_len; } - cmd.cmd_code = EC_CMD_I2C_PASSTHRU; - cmd.cmd_version = 0; - cmd.cmd_data_in = p; - cmd.cmd_size_in = size + write_len; - cmd.cmd_data_out = r; - cmd.cmd_size_out = sizeof(*r) + read_len; - cmd.cmd_dev_index = 0; + cmd = (struct chromeec_command){ + .cmd_code = EC_CMD_I2C_PASSTHRU, + .cmd_version = 0, + .cmd_data_in = p, + .cmd_size_in = size + write_len, + .cmd_data_out = r, + .cmd_size_out = sizeof(*r) + read_len, + .cmd_dev_index = 0, + }; rv = google_chromeec_command(&cmd); if (rv != 0) return rv; diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 131a460..37ea24a 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -154,6 +154,8 @@ uint16_t cmd_size_out; /* expected size of command response in, * actual received size out */ int cmd_dev_index;/* device index for passthru */ + uint32_t timeout_us; /* maximum time to wait for command completion + * or 0 for arbitrary default */ }; /* diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index a82ea5d..be801f6 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -91,15 +91,16 @@ return byte; } -static int google_chromeec_status_check(u16 port, u8 mask, u8 cond) +static int google_chromeec_status_check(u16 port, u8 mask, u8 cond, u32 timeout_us) { struct stopwatch timeout_sw; - /* One second is more than plenty for any EC operation to complete */ - const uint64_t ec_status_timeout_us = 1 * USECS_PER_SEC; + /* One second is more than plenty for most EC operations to complete */ + if (timeout_us == 0) + timeout_us = 1 * USECS_PER_SEC; /* Wait 1 usec between read attempts */ const uint64_t ec_status_read_period_us = 1; - stopwatch_init_usecs_expire(&timeout_sw, ec_status_timeout_us); + stopwatch_init_usecs_expire(&timeout_sw, timeout_us); do { if ((read_byte(port) & mask) == cond) return 0; @@ -108,18 +109,19 @@ return -1; } -static int google_chromeec_wait_ready(u16 port) +static int google_chromeec_wait_ready(u16 port, u32 timeout_us) { return google_chromeec_status_check(port, EC_LPC_CMDR_PENDING | - EC_LPC_CMDR_BUSY, 0); + EC_LPC_CMDR_BUSY, 0, + timeout_us); } #if CONFIG(EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) /* Read memmap data through ACPI port 66/62 */ static int read_memmap(u8 *data, u8 offset) { - if (google_chromeec_wait_ready(EC_LPC_ADDR_ACPI_CMD)) { + if (google_chromeec_wait_ready(EC_LPC_ADDR_ACPI_CMD, 0)) { printk(BIOS_ERR, "Timeout waiting for EC ready!\n"); return -1; } @@ -127,7 +129,7 @@ /* Issue the ACPI read command */ write_byte(EC_CMD_ACPI_READ, EC_LPC_ADDR_ACPI_CMD); - if (google_chromeec_wait_ready(EC_LPC_ADDR_ACPI_CMD)) { + if (google_chromeec_wait_ready(EC_LPC_ADDR_ACPI_CMD, 0)) { printk(BIOS_ERR, "Timeout waiting for EC READ_EVENT!\n"); return -1; } @@ -135,7 +137,7 @@ /* Write data address */ write_byte(offset + EC_ACPI_MEM_MAPPED_BEGIN, EC_LPC_ADDR_ACPI_DATA); - if (google_chromeec_wait_ready(EC_LPC_ADDR_ACPI_CMD)) { + if (google_chromeec_wait_ready(EC_LPC_ADDR_ACPI_CMD, 0)) { printk(BIOS_ERR, "Timeout waiting for EC DATA!\n"); return -1; } @@ -196,7 +198,7 @@ return -1; } - if (google_chromeec_wait_ready(EC_LPC_ADDR_HOST_CMD)) { + if (google_chromeec_wait_ready(EC_LPC_ADDR_HOST_CMD, 0)) { printk(BIOS_ERR, "Timeout waiting for EC start command %d!\n", cec_command->cmd_code); return -1; @@ -230,7 +232,7 @@ /* Start the command */ write_byte(EC_COMMAND_PROTOCOL_3, EC_LPC_ADDR_HOST_CMD); - if (google_chromeec_wait_ready(EC_LPC_ADDR_HOST_CMD)) { + if (google_chromeec_wait_ready(EC_LPC_ADDR_HOST_CMD, cec_command->timeout_us)) { printk(BIOS_ERR, "Timeout waiting for EC process command %d!\n", cec_command->cmd_code); return -1; @@ -307,7 +309,7 @@ /* Issue the command */ write_byte(cmd_code, EC_LPC_ADDR_HOST_CMD); - if (google_chromeec_wait_ready(EC_LPC_ADDR_HOST_CMD)) { + if (google_chromeec_wait_ready(EC_LPC_ADDR_HOST_CMD, cec_command->timeout_us)) { printk(BIOS_ERR, "Timeout waiting for EC process command %d!\n", cec_command->cmd_code); return 1; @@ -455,15 +457,15 @@ .enable_dev = enable_dev, }; -static int google_chromeec_data_ready(u16 port) +static int google_chromeec_data_ready(u16 port, u32 timeout_us) { return google_chromeec_status_check(port, EC_LPC_CMDR_DATA, - EC_LPC_CMDR_DATA); + EC_LPC_CMDR_DATA, timeout_us); } enum host_event_code google_chromeec_get_event(void) { - if (google_chromeec_wait_ready(EC_LPC_ADDR_ACPI_CMD)) { + if (google_chromeec_wait_ready(EC_LPC_ADDR_ACPI_CMD, 0)) { printk(BIOS_ERR, "Timeout waiting for EC ready!\n"); return EC_HOST_EVENT_NONE; } @@ -471,12 +473,12 @@ /* Issue the ACPI query-event command */ write_byte(EC_CMD_ACPI_QUERY_EVENT, EC_LPC_ADDR_ACPI_CMD); - if (google_chromeec_wait_ready(EC_LPC_ADDR_ACPI_CMD)) { + if (google_chromeec_wait_ready(EC_LPC_ADDR_ACPI_CMD, 0)) { printk(BIOS_ERR, "Timeout waiting for EC QUERY_EVENT!\n"); return EC_HOST_EVENT_NONE; } - if (google_chromeec_data_ready(EC_LPC_ADDR_ACPI_CMD)) { + if (google_chromeec_data_ready(EC_LPC_ADDR_ACPI_CMD, 0)) { printk(BIOS_ERR, "Timeout waiting for data ready!\n"); return EC_HOST_EVENT_NONE; } -- To view, visit https://review.coreboot.org/c/coreboot/+/63733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55d36479e680c34a8bff65776e7e295e94291342 Gerrit-Change-Number: 63733 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit April 2022