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Change subject: vendorcode/intel/fsp: Update FSP header file for Alder Lake N FSP v3133.00
......................................................................
Patch Set 3:
(1 comment)
File src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h:
https://review.coreboot.org/c/coreboot/+/63707/comment/67f8768e_1e428614
PS3, Line 2215: PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms
UFS description still not fixed by new FSP. Issue here https://partnerissuetracker.corp.google.com/issues/228110908
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Change subject: mb/google/brya/var/taeko: Add WIFI SAR support for tarlo
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Patch Set 6: Code-Review+2
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Change subject: mb/google/nipperkin: Fix WLAN to GEN2 speed
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/guybrush/variants/nipperkin/variant.c:
https://review.coreboot.org/c/coreboot/+/63722/comment/82a47cd8_97d0f8b4
PS1, Line 12: sizeof(dxio_descriptors[WLAN].port_params));
Hi Rob,
so maybe we need to remove these since RP is config AC/DC to GEN2 in this patch? thanks.
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Change subject: mb/google/brya/var/brya0: Swap TPM and touchscreen I2C bus
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Change subject: soc/intel/jasperlake: Enable fewer wakeups to reduce SoC power consumption
......................................................................
Patch Set 4:
(9 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63675/comment/09bc2c49_aea90811
PS3, Line 7: soc/intel/jasperlake: Add a workaround for cnvi
> Maybe: […]
keep the prefix because this is for JSL only.
https://review.coreboot.org/c/coreboot/+/63675/comment/f86c97bc_746b7556
PS3, Line 9: add a workaround to mitigate
: the higher SoC power consumption in S0iX
> … work around higher SoC power consumption in S0iX, when CNVI has background activity.
Done
https://review.coreboot.org/c/coreboot/+/63675/comment/a55ebaa0_76bc4573
PS3, Line 15: Those settings are correct.
> Please add the exact power consumption values.
The exact power consumption value is not a fixed value.
It depends on what kind of background activity.
File src/soc/intel/jasperlake/chip.h:
https://review.coreboot.org/c/coreboot/+/63675/comment/5de463ae_dd04cc8d
PS3, Line 430: AC9560(JfP2)
> Please add a space before the (.
Done
https://review.coreboot.org/c/coreboot/+/63675/comment/1c2d57c7_0f426076
PS3, Line 430: chipsets :
> Please remove the space before the colon.
Done
https://review.coreboot.org/c/coreboot/+/63675/comment/31b23c6a_17254b78
PS3, Line 431: AX201(HrP2)
> Ditto.
Done
https://review.coreboot.org/c/coreboot/+/63675/comment/da3a697e_d9ed7533
PS3, Line 433: 1: Enabled(fewer wakes, lower power); 0: Disabled(more wakes, higher power)
> Please use true/false, and add a space before the (.
Done
https://review.coreboot.org/c/coreboot/+/63675/comment/7ed429b6_4fdba0c5
PS3, Line 435: bool cnvi_s0ix_wa;
> Add “power usage” or something similar to the name?
Done
File src/soc/intel/jasperlake/finalize.c:
https://review.coreboot.org/c/coreboot/+/63675/comment/021eee96_ad0a38bb
PS3, Line 65: (1 << 0)
> possible to create a macro?
Use the BIT macro here.
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Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Tim Wawrzynczak, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/jasperlake: Enable fewer wakeups to reduce SoC power consumption
......................................................................
soc/intel/jasperlake: Enable fewer wakeups to reduce SoC power consumption
According to Intel TA#724456, work around the higher SoC power
consumption in S0iX when CNVI has background activity.
BUG=b:201263040
TEST=Turn on this setting and build and verify on Drawcia.
The SLP_S0 toggling become slower or gone at the same CNVI
background activity.
Change-Id: I56439a406547e2ee1e47d34be14ecc9a8df04693
Signed-off-by: Jamie Chen <jamie.chen(a)intel.com>
---
M src/soc/intel/jasperlake/chip.h
M src/soc/intel/jasperlake/finalize.c
M src/soc/intel/jasperlake/include/soc/pmc.h
3 files changed, 23 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/63675/4
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Change subject: mb/google/brya/var/brya0: Swap TPM and touchscreen I2C bus
......................................................................
mb/google/brya/var/brya0: Swap TPM and touchscreen I2C bus
Based on the latest schematic, exchange I2C port for TPM/touchscreen.
TPM: I2C3 -> I2C1
Touchscreen: I2C1 -> I2C3
BUG=b:202671753
TEST=emerge-brya coreboot
Change-Id: Ifa6235869f34e0038a8ecad33d59654626cf7815
Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/variants/brya0/gpio.c
M src/mainboard/google/brya/variants/brya0/overridetree.cb
3 files changed, 159 insertions(+), 63 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/63709/4
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Change subject: mb/google/brya/var/brya0: Swap TPM and touchscreen I2C bus
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Patch Set 3: Code-Review+2
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