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Change subject: mb/google/brya/var/taeko: Add WIFI SAR support for tarlo
......................................................................
mb/google/brya/var/taeko: Add WIFI SAR support for tarlo
Taeko/Tarlo uses the WIFI_SAR_ID field in FW_CONFIG to pick which
SAR table to load.
BUG=b:226684990
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M src/mainboard/google/brya/variants/taeko/variant.c
1 file changed, 6 insertions(+), 1 deletion(-)
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Change subject: mb/google/brya/var/crota: update gpio configuration
......................................................................
Patch Set 2: Code-Review+2
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Hello build bot (Jenkins), Tim Wawrzynczak, Eric Lai,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya/var/crota: modify DQ/ DQS table
......................................................................
mb/google/brya/var/crota: modify DQ/ DQS table
BUG=b:229547171
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---
M src/mainboard/google/brya/variants/crota/memory.c
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Change subject: mb/google/brya/var/crota: limit dram speed at 4800
......................................................................
Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63682/comment/aac6bc30_e6dbb5d2
PS3, Line 9: For tyep-3 PCB board
> suggestion: […]
Done
Patchset:
PS3:
> suggestion, if this is only limited on certain sku, you can use variant.c to update it.
Got it. This need to be apply to all sku. Thanks.
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Change subject: mb/google/brya/var/crota: limit dram speed at 4800
......................................................................
mb/google/brya/var/crota: limit dram speed at 4800
When using LPDDR5 on a Type-C PCB, the Intel PDG recommends
a maximum DRAM speed of 4800 MT/s.
BUG=b:229549930
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---
M src/mainboard/google/brya/variants/crota/overridetree.cb
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Change subject: mb/google/brya/var/crota: limit dram speed at 4800
......................................................................
mb/google/brya/var/crota: limit dram speed at 4800
For tyep-3 PCB board, the dram speed must not higher than 4800.
BUG=b:229549930
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Change subject: mb/google/brya/var/crota: enable boot from SSD/ eMMC
......................................................................
mb/google/brya/var/crota: enable boot from SSD/ eMMC
- Fix eMMC reset/ enable GPIO pins.
- Fix clk_req and clk_src
BUG=b:229437061
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Change subject: mb/google/brya/var/crota: update gpio configuration
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63713/comment/5f9a054a_06937a40
PS1, Line 7: corta
> `crota`
Done
https://review.coreboot.org/c/coreboot/+/63713/comment/063e3993_a0e19f6c
PS1, Line 7: mb/google/brya/var/corta: enable CPU PCIe VGPIO
> change title maybe just update gpio table. the CL not only change CPU PCIE RP.
Done
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