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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/common: Fix buggy code tries to access DESC region
......................................................................
soc/intel/common: Fix buggy code tries to access DESC region
The patch fixes the buggy code which tries to access the Descriptor
Region.
TEST=Build and verify no errors seen while accessing the Descriptor
Region.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: Ib144cc0845b7527e5a3032529b0802f961944b87
---
M src/soc/intel/common/basecode/debug/debug_feature.c
1 file changed, 3 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/63734/2
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Change subject: mb/google/brya/var/taniks: Configure Acoustic noise mitigation
......................................................................
Patch Set 2:
This change is ready for review.
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Change subject: soc/intel/alderlake: Implement PMC feature lock
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/alderlake/lockdown.c:
https://review.coreboot.org/c/coreboot/+/63691/comment/1aeca627_23046b22
PS4, Line 28: setbits32(pmc_mmio_regs() + PM_CFG, PM_CFG_DBG_MODE_LOCK |
> > Will add more settings? Maybe create a structure to maintain it? If just 3, it's fine. […]
Yes, this is what I mean. And we can use #ifdef CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM) in structure, to make it optimize in built time. I don't expect it will be a lot need to skip.
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Change subject: soc/intel/alderlake: Implement PMC feature lock
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/alderlake/lockdown.c:
https://review.coreboot.org/c/coreboot/+/63691/comment/ecdaef5f_afe6af60
PS4, Line 28: setbits32(pmc_mmio_regs() + PM_CFG, PM_CFG_DBG_MODE_LOCK |
> Will add more settings? Maybe create a structure to maintain it? If just 3, it's fine.
actually I have thought of adding a structure of this entire function as we are just doing the `setbits32()` .
Something like this https://github.com/coreboot/coreboot/blob/master/src/soc/intel/common/block…
but we have several `if` clauses to skip the programmed hence, need to add a `skip` variable as well part of the structure, it would make it complicated eventually and as Arthur said in one CL, having a `skip` structure variable might not serve well the compiler optimisation part.
WDYT about this.
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Change subject: intel/common/../systemagent: Add sa_get_mchbar_base api
......................................................................
Patch Set 8:
(2 comments)
File src/soc/intel/common/block/systemagent/systemagent_early.c:
https://review.coreboot.org/c/coreboot/+/63615/comment/4cc4b1fb_dbefee6f
PS8, Line 89: if (mchbar_lo & 0x1)
what if mchbar_lo and hi value is zero and BAR enable bit is set? we would run into the problem isn't it ?
https://review.coreboot.org/c/coreboot/+/63615/comment/f499c055_cd823d30
PS8, Line 92:
tab ?
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Change subject: mb/prodrive/atlas: Enable PCH PCIe RP7
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63718/comment/58f669c4_b854475f
PS1, Line 7: PR7
> RP7
Done
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Change subject: soc/amd/picasso: Use read*p
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
File src/soc/amd/common/block/cpu/smm/smi_apmc_helper.c:
https://review.coreboot.org/c/coreboot/+/63726/comment/cf753558_7689a334
PS3, Line 85: size_t
Why not `uintptr_t`?
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I'd like you to reexamine a change. Please visit
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Change subject: mb/prodrive/atlas: Enable PCH PCIe RP7
......................................................................
mb/prodrive/atlas: Enable PCH PCIe RP7
Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com>
Change-Id: I3f438a7b1dff1a44a81edc8adc983d08708fdd57
---
M src/mainboard/prodrive/atlas/devicetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/63718/2
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Change subject: cpu/x86/64bit: Generate static page tables from an assembly file
......................................................................
Patch Set 3: Code-Review+1
(2 comments)
Patchset:
PS3:
Couldn't one generate the assembly file at build time using a tool?
File src/cpu/x86/64bit/pt.S:
https://review.coreboot.org/c/coreboot/+/63725/comment/4fb4b570_f570f9c4
PS3, Line 4: ArchitectureProgrammer
nit: missing a space
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Change subject: soc/intel/alderlake: Refactor `pmc_lockdown_cfg` function
......................................................................
Patch Set 1: Code-Review+2
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