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Change subject: apple/macbook21: configure the clockgen and add C3 CPU state
......................................................................
Patch Set 9:
(2 comments)
Patchset:
PS6:
> the override devicetree will be needed for both mackbook11 and macbook21, since the c3 state is only […]
I hope the new patchset fixes that
File src/mainboard/apple/macbook21/cstates.c:
https://review.coreboot.org/c/coreboot/+/63587/comment/e89c8422_bc299f8c
PS4, Line 34: .latency = 17,
> 1 likely isn't a good value here; 17 will work and is also what one of the lenovo laptops uses here. […]
I'll maybe do that later. I'll mark the discussion as solved but
will have that in my TODO list.
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Change subject: arch/x86/postcar: Set up postcar MTRR in C code
......................................................................
Patch Set 13:
(1 comment)
File src/soc/amd/common/block/cpu/noncar/early_cache.c:
https://review.coreboot.org/c/coreboot/+/54299/comment/da0e1487_2c5f46a8
PS13, Line 13: * We don't know the amount of variable mtrr's to preallocate space on the stack.
*for* in the end?
… to preallocate space on the stack for.
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Change subject: tpm: Allow separate handling of Google Ti50 TPM
......................................................................
Patch Set 14:
(2 comments)
File src/drivers/i2c/tpm/cr50.c:
https://review.coreboot.org/c/coreboot/+/63158/comment/e869f092_e2f02987
PS14, Line 506: TPM_CR50
`TPM_GOOGLE_CR50`
File src/mainboard/google/brya/Kconfig:
https://review.coreboot.org/c/coreboot/+/63158/comment/9011b889_56140486
PS14, Line 47: TI50
`CR50`, Nissa is the only baseboard here that uses ti50
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Change subject: mb/purism/librem_mini: Rework front status LED to show all disk activity
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
File src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/acpi/variant.asl:
PS1:
If you're bored, a drivers/generic/gpio_leds chip driver to generate the AML might be nice to have 😎
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Change subject: soc/intel/adl/chip.h: add unit in max_dram_speed
......................................................................
Patch Set 2: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63735/comment/ebb5f7e3_932fc6bc
PS2, Line 9: on
to
Patchset:
PS2:
Thank you!
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Change subject: apple/macbook21: configure the clockgen and add C3 CPU state
......................................................................
Patch Set 8:
(2 comments)
Patchset:
PS6:
> Was the latest version tested? It seems `config OVERRIDE_DEVICETREE` […]
the override devicetree will be needed for both mackbook11 and macbook21, since the c3 state is only not added for the imac52, so the two macbook will need the proper clockgen configuration
File src/mainboard/apple/macbook21/cstates.c:
https://review.coreboot.org/c/coreboot/+/63587/comment/2ee770ff_b82cf99d
PS4, Line 34: .latency = 17,
> That sounds like a good idea too.
1 likely isn't a good value here; 17 will work and is also what one of the lenovo laptops uses here. not sure if the vendor firmware uses some other number and it probably doesn't need to be the exact number from the vendor firmware for this to work; the value is likely some trade-off between power savings and performance. i won't complain if you just keep the 17 and mark this discussion as solved, but the best way would probably be to look at the ACPI tables from the vendor firmware and get the values from there
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63440 )
Change subject: mb/google/brya/var/vell: increase RFI Spread Spectrum to 6%
......................................................................
mb/google/brya/var/vell: increase RFI Spread Spectrum to 6%
Increase RFI Spread Spectrum to 6% for Vell as RF team request. The
default of Spread Spectrum in FSP is 1.5%, and set 1.5% in baseboard
as default.
BUG=b:228929196
TEST=emerge-brya coreboot and pass RF test as before
Change-Id: I7cdca8f51ad18f4ab03e4e6c744b60da68263ce2
Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63440
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---
M src/mainboard/google/brya/variants/vell/overridetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb
index fd5f27a..a2fe72d 100644
--- a/src/mainboard/google/brya/variants/vell/overridetree.cb
+++ b/src/mainboard/google/brya/variants/vell/overridetree.cb
@@ -71,6 +71,9 @@
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"
register "sagv" = "SaGv_Enabled"
+ # FIVR RFI Spread Spectrum 6%
+ register "fivr_spread_spectrum" = "FIVR_SS_6"
+
# I2C Port Config
register "serial_io_i2c_mode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
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