coreboot-gerrit April 2022

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Change in coreboot[master]: mb/google/skyrim: Update SPI settings for skyrim
by Karthik Ramasubramanian (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Raul Rangel, Jon Murphy, Chris Wang, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63717 ) Change subject: mb/google/skyrim: Update SPI settings for skyrim ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63717 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbe4b9f4794f7e883c3819258ede809c3c8922b0 Gerrit-Change-Number: 63717 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 20 Apr 2022 16:48:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/64bit: Generate static page tables from an assembly file
by Raul Rangel (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Patrick Rudolph, Arthur Heymans. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63725 ) Change subject: cpu/x86/64bit: Generate static page tables from an assembly file ...................................................................... Patch Set 3: (2 comments) File src/cpu/x86/64bit/pt.S: https://review.coreboot.org/c/coreboot/+/63725/comment/f5671572_8664097f PS3, Line 27: .quad _GEN_PAGE(0x200000 * 0) > > > Can you use a macro to reduce the duplication? […] I was wondering if there was a recursion limit. Thanks for trying. I think it's fine as is. File src/cpu/x86/Makefile.inc: https://review.coreboot.org/c/coreboot/+/63725/comment/1f821ead_c7980acc PS3, Line 7: CONFIG_ARCH_BOOTBLOCK_X86_64 > > Should we add lines for all the different stages instead of assuming? […] I guess I'm concerned about the PSP Verstage case. Not sure if the ``` all-y += mode_switch.S ``` will work for us. Maybe that's the part that needs the individual rules? -- To view, visit https://review.coreboot.org/c/coreboot/+/63725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1e31b701a2584268c85d327bf139953213899e3 Gerrit-Change-Number: 63725 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 20 Apr 2022 16:46:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/64bit: Generate static page tables from an assembly file
by Arthur Heymans (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Raul Rangel, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63725 ) Change subject: cpu/x86/64bit: Generate static page tables from an assembly file ...................................................................... Patch Set 3: (1 comment) File src/cpu/x86/64bit/pt.S: https://review.coreboot.org/c/coreboot/+/63725/comment/d9d9df5a_6ebafb50 PS3, Line 27: .quad _GEN_PAGE(0x200000 * 0) > > > Can you use a macro to reduce the duplication? > > > > > > https://sourceware.org/binutils/docs/as/Macro.html > > > > I'll try. > > Sadly 100 is the max amount of nested macros allowed. Let's see if it's possible to improve that... The max is hardcoded. We can patch binutils but then it becomes impossible to compile coreboot with older and external toolchains. I guess this is the best we can do... -- To view, visit https://review.coreboot.org/c/coreboot/+/63725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1e31b701a2584268c85d327bf139953213899e3 Gerrit-Change-Number: 63725 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Wed, 20 Apr 2022 16:45:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/64bit: Generate static page tables from an assembly file
by Arthur Heymans (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Raul Rangel, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63725 ) Change subject: cpu/x86/64bit: Generate static page tables from an assembly file ...................................................................... Patch Set 3: (1 comment) File src/cpu/x86/64bit/pt.S: https://review.coreboot.org/c/coreboot/+/63725/comment/2ea66529_2f3b2eca PS3, Line 27: .quad _GEN_PAGE(0x200000 * 0) > > Can you use a macro to reduce the duplication? > > > > https://sourceware.org/binutils/docs/as/Macro.html > > I'll try. Sadly 100 is the max amount of nested macros allowed. Let's see if it's possible to improve that... -- To view, visit https://review.coreboot.org/c/coreboot/+/63725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1e31b701a2584268c85d327bf139953213899e3 Gerrit-Change-Number: 63725 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Wed, 20 Apr 2022 16:42:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: docs/coding_style: Clarify use of GCC extensions
by Julius Werner (Code Review) 20 Apr '22

20 Apr '22

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63660 ) Change subject: docs/coding_style: Clarify use of GCC extensions ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > Is there value in a section on what to do if a developer encounters a GCC extension that their compi […] I mean, that would only be applicable to HOSTCC code, I think... for coreboot code I think it's well-established that crossgcc is the only compiler we care about and we should keep it that way. (The folks that care about clang should figure out how they want that to work once it is more stable... without integrating anything into Jenkins it's going to be hard to keep any support working long term.) It would certainly not hurt to have more documentation on crossgcc and general compiler expectations, but I think at that point it's getting pretty far away from "coding style"... maybe that would fit better somewhere under getting_started. -- To view, visit https://review.coreboot.org/c/coreboot/+/63660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d0eb90d6729fefeb131cdd573ad51f1884afe11 Gerrit-Change-Number: 63660 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 20 Apr 2022 16:41:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/brya0: configure gpio for headset
by Tim Wawrzynczak (Code Review) 20 Apr '22

20 Apr '22

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63721 ) Change subject: mb/google/brya/var/brya0: configure gpio for headset ...................................................................... mb/google/brya/var/brya0: configure gpio for headset Configure GPP_R0, GPP_R1, GPP_R2 and GPP_R3 for headset function enable with ALC5682I+MAX98360. BUG=b:202671753 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I93070a8096d43557a50e5a545227f2906e299d8e Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63721 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/brya0/fw_config.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Frank Wu: Looks good to me, approved Tim Wawrzynczak: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/brya0/fw_config.c b/src/mainboard/google/brya/variants/brya0/fw_config.c index 8113627..c2b963f 100644 --- a/src/mainboard/google/brya/variants/brya0/fw_config.c +++ b/src/mainboard/google/brya/variants/brya0/fw_config.c @@ -144,7 +144,7 @@ printk(BIOS_INFO, "Configure audio over I2S with MAX98360 ALC5682I.\n"); gpio_configure_pads(max98360_enable_pads, ARRAY_SIZE(max98360_enable_pads)); printk(BIOS_INFO, "BT offload enabled\n"); - gpio_configure_pads(i2s0_disable_pads, ARRAY_SIZE(i2s0_disable_pads)); + gpio_configure_pads(i2s0_enable_pads, ARRAY_SIZE(i2s0_enable_pads)); gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads)); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/63721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93070a8096d43557a50e5a545227f2906e299d8e Gerrit-Change-Number: 63721 Gerrit-PatchSet: 2 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/brya0: configure gpio for headset
by Tim Wawrzynczak (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Amanda Hwang, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63721 ) Change subject: mb/google/brya/var/brya0: configure gpio for headset ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > This is for I2S headset function and apply with new fw_config. […] 👍 -- To view, visit https://review.coreboot.org/c/coreboot/+/63721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93070a8096d43557a50e5a545227f2906e299d8e Gerrit-Change-Number: 63721 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 20 Apr 2022 16:31:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/brya0: Swap TPM and touchscreen I2C bus
by Tim Wawrzynczak (Code Review) 20 Apr '22

20 Apr '22

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63709 ) Change subject: mb/google/brya/var/brya0: Swap TPM and touchscreen I2C bus ...................................................................... mb/google/brya/var/brya0: Swap TPM and touchscreen I2C bus Based on the latest schematic, exchange I2C port for TPM/touchscreen. TPM: I2C3 -> I2C1 Touchscreen: I2C1 -> I2C3 BUG=b:202671753 TEST=emerge-brya coreboot Change-Id: Ifa6235869f34e0038a8ecad33d59654626cf7815 Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63709 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/brya0/gpio.c M src/mainboard/google/brya/variants/brya0/overridetree.cb 3 files changed, 159 insertions(+), 63 deletions(-) Approvals: build bot (Jenkins): Verified Frank Wu: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 24a606c..122e992 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -92,7 +92,7 @@ config DRIVER_TPM_I2C_BUS hex - default 0x3 if BOARD_GOOGLE_BRYA0 + default 0x1 if BOARD_GOOGLE_BRYA0 default 0x3 if BOARD_GOOGLE_BRYA4ES default 0x1 if BOARD_GOOGLE_BRASK default 0x1 if BOARD_GOOGLE_PRIMUS diff --git a/src/mainboard/google/brya/variants/brya0/gpio.c b/src/mainboard/google/brya/variants/brya0/gpio.c index 4cf99df..251348b 100644 --- a/src/mainboard/google/brya/variants/brya0/gpio.c +++ b/src/mainboard/google/brya/variants/brya0/gpio.c @@ -117,6 +117,52 @@ PAD_NC(GPP_H13, UP_20K), }; +/* Early pad configuration in bootblock for board id 4 */ +static const struct pad_config early_gpio_table_id4[] = { + /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_A12, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* H6 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* + * D1 : ISH_GP1 ==> FP_RST_ODL + * FP_RST_ODL comes out of reset as hi-z and does not have an external + * pull-down. To ensure proper power sequencing for the FPMCU device, + * reset signal is driven low early on in bootblock, followed by + * enabling of power. Reset signal is deasserted later on in ramstage. + * Since reset signal is asserted in bootblock, it results in FPMCU not + * working after a S3 resume. This is a known issue. + */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */ + PAD_CFG_GPO(GPP_E0, 0, DEEP), + /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */ + PAD_CFG_GPO(GPP_E16, 0, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_NC(GPP_H13, UP_20K), +}; + static const struct pad_config romstage_gpio_table[] = { /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 1, DEEP), @@ -142,6 +188,9 @@ if (id == BOARD_ID_UNKNOWN || id < 2) { *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; + } else if (id >= 4) { + *num = ARRAY_SIZE(early_gpio_table_id4); + return early_gpio_table_id4; } *num = ARRAY_SIZE(early_gpio_table_id2); diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index fd8224c..6f0eb21 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -52,6 +52,53 @@ .configure_ext_fivr = 1, }" + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C2 | SAR | + #| I2C3 | TouchScreen | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 900, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + }" + device domain 0 on device ref dtt on chip drivers/intel/dptf @@ -359,62 +406,12 @@ end end #I2C0 device ref i2c1 on - chip drivers/i2c/hid - register "generic.hid" = ""ELAN9050"" - register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" - register "generic.reset_delay_ms" = "300" - register "generic.reset_off_delay_ms" = "1" - register "generic.enable_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" - register "generic.enable_delay_ms" = "6" - register "generic.stop_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" - register "generic.stop_off_delay_ms" = "1" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 0x10 on end + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end end - chip drivers/i2c/hid - register "generic.hid" = ""GDIX0000"" - register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" - register "generic.reset_delay_ms" = "120" - register "generic.reset_off_delay_ms" = "3" - register "generic.enable_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" - register "generic.enable_delay_ms" = "12" - register "generic.stop_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" - register "generic.stop_off_delay_ms" = "1" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 0x5d on end - end - chip drivers/i2c/hid - register "generic.hid" = ""SIS9815"" - register "generic.desc" = ""SIS Touchscreen"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" - register "generic.stop_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" - register "generic.stop_delay_ms" = "100" - register "generic.enable_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" - register "generic.enable_delay_ms" = "7" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x00" - device i2c 5c on end - end - end + end #I2C1 device ref i2c2 on chip drivers/i2c/sx9324 register "desc" = ""SAR1 Proximity Sensor"" @@ -584,14 +581,64 @@ probe HPS HPS_PRESENT end end - end + end #I2C2 device ref i2c3 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" - device i2c 50 on end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9050"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "300" + register "generic.reset_off_delay_ms" = "1" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "6" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x10 on end end - end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "12" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x5d on end + end + chip drivers/i2c/hid + register "generic.hid" = ""SIS9815"" + register "generic.desc" = ""SIS Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_delay_ms" = "100" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "7" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x00" + device i2c 5c on end + end + end #I2C3 device ref i2c5 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" @@ -601,7 +648,7 @@ register "probed" = "1" device i2c 15 on end end - end + end #I2C5 device ref hda on chip drivers/generic/max98357a register "hid" = ""MX98357A"" -- To view, visit https://review.coreboot.org/c/coreboot/+/63709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa6235869f34e0038a8ecad33d59654626cf7815 Gerrit-Change-Number: 63709 Gerrit-PatchSet: 5 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: Revert "mb/google/guybrush/var/dewatt: Override SPI fast speed"
by Karthik Ramasubramanian (Code Review) 20 Apr '22

20 Apr '22

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63746 ) Change subject: Revert "mb/google/guybrush/var/dewatt: Override SPI fast speed" ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Submitted it since this is required for board version 2 to boot reliably and avoid any flakiness. -- To view, visit https://review.coreboot.org/c/coreboot/+/63746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b6acd2cda2af35ff33e89e3b339731e35d72cb1 Gerrit-Change-Number: 63746 Gerrit-PatchSet: 2 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 20 Apr 2022 16:14:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: Revert "mb/google/guybrush/var/dewatt: Override SPI fast speed"
by Karthik Ramasubramanian (Code Review) 20 Apr '22

20 Apr '22

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63746 ) Change subject: Revert "mb/google/guybrush/var/dewatt: Override SPI fast speed" ...................................................................... Revert "mb/google/guybrush/var/dewatt: Override SPI fast speed" This reverts commit d80d88c0fec96b2fff93db87d0c83f4c6754ae7a. Reason for revert: 100Mhz should only be enabled on DeWatt on board version >=3. Enabling it on board version 2 will cause failures. BUG=b:213403891 BRANCH=guybrush TEST=Build dewatt Change-Id: I0b6acd2cda2af35ff33e89e3b339731e35d72cb1 Signed-off-by: Rob Barnes <robbarnes(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63746 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/guybrush/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Raul Rangel: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index a49f586..16deda5 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -137,7 +137,7 @@ config OVERRIDE_EFS_SPI_SPEED_MIN_BOARD hex default 0x4 if BOARD_GOOGLE_GUYBRUSH - default 0x2 if BOARD_GOOGLE_NIPPERKIN || BOARD_GOOGLE_DEWATT + default 0x2 if BOARD_GOOGLE_NIPPERKIN default 0xffffffff help Minimum board version starting which the Override EFS SPI Speed -- To view, visit https://review.coreboot.org/c/coreboot/+/63746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b6acd2cda2af35ff33e89e3b339731e35d72cb1 Gerrit-Change-Number: 63746 Gerrit-PatchSet: 2 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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