coreboot-gerrit April 2022

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Change in coreboot[master]: mb/prodrive/atlas: Enable UFS and ISH
by Felix Held (Code Review) 20 Apr '22

20 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63719 ) Change subject: mb/prodrive/atlas: Enable UFS and ISH ...................................................................... mb/prodrive/atlas: Enable UFS and ISH The PCI Local Bus Specification Revision 3.0 requires that multi-function devices always implement function 0. Because of this, enabling UFS (PCI device 12.7) requires ISH (PCI device 12.0) to be enabled as well. Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: Ia8b9561973640edc5f7d0f579dd640e805c0af17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63719 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/prodrive/atlas/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb index df00c7d..0170fc2 100644 --- a/src/mainboard/prodrive/atlas/devicetree.cb +++ b/src/mainboard/prodrive/atlas/devicetree.cb @@ -90,6 +90,8 @@ device ref pcie4_0 on end device ref pcie4_1 on end device ref crashlog off end + device ref ish on end + device ref ufs on end device ref xhci on end device ref heci1 on end device ref sata on end -- To view, visit https://review.coreboot.org/c/coreboot/+/63719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8b9561973640edc5f7d0f579dd640e805c0af17 Gerrit-Change-Number: 63719 Gerrit-PatchSet: 2 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/prodrive/atlas: Enable PCH PCIe RP7
by Felix Held (Code Review) 20 Apr '22

20 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63718 ) Change subject: mb/prodrive/atlas: Enable PCH PCIe RP7 ...................................................................... mb/prodrive/atlas: Enable PCH PCIe RP7 Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: I3f438a7b1dff1a44a81edc8adc983d08708fdd57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63718 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/prodrive/atlas/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb index 63c34ad..df00c7d 100644 --- a/src/mainboard/prodrive/atlas/devicetree.cb +++ b/src/mainboard/prodrive/atlas/devicetree.cb @@ -95,6 +95,7 @@ device ref sata on end device ref pcie_rp5 on end device ref pcie_rp6 on end + device ref pcie_rp7 on end device ref pcie_rp8 on end device ref pcie_rp9 on end device ref pcie_rp10 on end 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63718 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f438a7b1dff1a44a81edc8adc983d08708fdd57 Gerrit-Change-Number: 63718 Gerrit-PatchSet: 3 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: intel/common/../systemagent: Add sa_get_mchbar_base api
by Angel Pons (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Wonkyu Kim, Paul Menzel. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63615 ) Change subject: intel/common/../systemagent: Add sa_get_mchbar_base api ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: Oof, this sounds way too inefficient. What's wrong with enabling MCHBAR in bootblock? One could even have a `SOC_INTEL_COMMON_SA_MCHBAR_IN_BOOTBLOCK` Kconfig to decide when to enable MCHBAR. -- To view, visit https://review.coreboot.org/c/coreboot/+/63615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4c7af3ea8c2b2b6afcc76e1165fadbe15e0bceb Gerrit-Change-Number: 63615 Gerrit-PatchSet: 8 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 20 Apr 2022 19:23:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Enable UFS and ISH for ADL-N RVP
by Angel Pons (Code Review) 20 Apr '22

20 Apr '22

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62662 ) Change subject: mb/intel/adlrvp: Enable UFS and ISH for ADL-N RVP ...................................................................... mb/intel/adlrvp: Enable UFS and ISH for ADL-N RVP In order to enable the UFS controller (PCI device 12.7), the PCI specification says that the device at function 0 in the same slot must also be enabled, which is the ISH. Therefore, this CL enables both the UFS controller and ISH. TEST=Boot to kernel and check lspci output 00:12.0 Serial controller: Intel Corporation Device 54fc 00:12.7 Mass storage controller [0109]: Intel Corporation Device 54ff Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Change-Id: If15bcaffc8fd3bbbe4b181820993ab2d882bbbe1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62662 Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/adlrvp/devicetree_n.cb 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Lean Sheng Tan: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Kangheui Won: Looks good to me, but someone else must approve diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb index 57a3701..40dba8b 100644 --- a/src/mainboard/intel/adlrvp/devicetree_n.cb +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -270,6 +270,8 @@ device ref gspi0 on end device ref p2sb on end device ref emmc on end + device ref ish on end + device ref ufs on end device ref hda on chip drivers/intel/soundwire device generic 0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/62662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If15bcaffc8fd3bbbe4b181820993ab2d882bbbe1 Gerrit-Change-Number: 62662 Gerrit-PatchSet: 8 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniil Lunev <dlunev(a)chromium.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/purism/librem_mini: Rework front status LED to show all disk activity
by Angel Pons (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Matt DeVillier, Tim Wawrzynczak. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63749 ) Change subject: mb/purism/librem_mini: Rework front status LED to show all disk activity ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: Interesting, do other OSes work with this? -- To view, visit https://review.coreboot.org/c/coreboot/+/63749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34c2a5f3fd1038266f4514544abfc1020da6f85b Gerrit-Change-Number: 63749 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 20 Apr 2022 19:17:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/purism/librem_mini: Rework front status LED to show all disk activity
by Matt DeVillier (Code Review) 20 Apr '22

20 Apr '22

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63749 ) Change subject: mb/purism/librem_mini: Rework front status LED to show all disk activity ...................................................................... mb/purism/librem_mini: Rework front status LED to show all disk activity The front status LED on the Librem Mini is driven by the SATALED# GPIO line configured for native function, so only shows disk activity for SATA drives, but not NVMe. To allow it to show disk activity for NVMe drives as well, reconfigure the GPIO as GPIO-OUT (rather than native function), and configure it via ACPI so that the linux gpio-leds driver will attach and use it accordingly. This has the added benefit of allowing the user to reconfigure the LED as they see fit via sysfs. Test: boot PureOS on Librem Mini v2 with NVMe drive, observe status LED blinks during periods of disk activity (tested via 'stress'). Change-Id: I34c2a5f3fd1038266f4514544abfc1020da6f85b Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c M src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/acpi/variant.asl 2 files changed, 53 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/63749/1 diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c index 08134e0..24ed2be 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c @@ -539,8 +539,8 @@ /* GPP_E7 - NC */ PAD_NC(GPP_E7, NONE), - /* GPP_E8 - SATALED# */ - PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + /* GPP_E8 - STATUSLED# */ + PAD_CFG_GPO(GPP_E8, 1, PLTRST), /* GPP_E9 - USB2_OC0# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/acpi/variant.asl b/src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/acpi/variant.asl index 0c9a76b..a3b852b 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/acpi/variant.asl +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/acpi/variant.asl @@ -14,3 +14,54 @@ } } } + +Scope (\_SB) +{ + Device (LEDS) + { + Name (_HID, "PRP0001") + Name (_DDN, "GPIO LEDs device") + + Name (_CRS, ResourceTemplate () { + GpioIo ( + Exclusive, // Not shared + PullNone, // No need for pulls + 0, // Debounce timeout + 0, // Drive strength + IoRestrictionOutputOnly, // Only used as output + "\\_SB.PCI0.GPIO", // GPIO controller + 0) // Must be 0 + { + 296, // GPP_E8 - STATUSLED# + } + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "compatible", Package() { "gpio-leds" } }, + }, + ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package () { + Package () {"led-0", "LED0"}, + } + }) + + /* + * For more information about these bindings see: + * Documentation/devicetree/bindings/leds/common.yaml, + * Documentation/devicetree/bindings/leds/leds-gpio.yaml and + * Documentation/firmware-guide/acpi/gpio-properties.rst. + */ + Name (LED0, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"label", "blue:status"}, + Package () {"default-state", "keep"}, + Package () {"linux,default-trigger", "disk-activity"}, + Package () {"gpios", Package () {^LEDS, 0, 0, 1}}, + Package () {"retain-state-suspended", 1}, + } + }) + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/63749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34c2a5f3fd1038266f4514544abfc1020da6f85b Gerrit-Change-Number: 63749 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration
by Angel Pons (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Marc Jones, Subrata Banik, Tim Wawrzynczak, Arthur Heymans, Eric Lai, Lean Sheng Tan. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63630 ) Change subject: soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration ...................................................................... Patch Set 6: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63630/comment/a0b89a60_57d37e61 PS4, Line 14: configuration register offset 0xDC bits BILD and LE are set. > @Angel, any more thoughts ? OK, if there's no hang it should be OK. -- To view, visit https://review.coreboot.org/c/coreboot/+/63630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e49b783e5db0ff40238e6e9259e48a4ecca66f8 Gerrit-Change-Number: 63630 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 20 Apr 2022 19:01:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration
by Subrata Banik (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Marc Jones, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63630 ) Change subject: soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63630/comment/289c0db3_5b9b8d3f PS4, Line 14: configuration register offset 0xDC bits BILD and LE are set. > > Could you please test what happens after setting the WPD bit from the OS? For example, using setpc […] @Angel, any more thoughts ? -- To view, visit https://review.coreboot.org/c/coreboot/+/63630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e49b783e5db0ff40238e6e9259e48a4ecca66f8 Gerrit-Change-Number: 63630 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 20 Apr 2022 18:36:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl/chip.h: add unit in max_dram_speed
by Tim Wawrzynczak (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Paul Menzel, Scott Chao. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63735 ) Change subject: soc/intel/adl/chip.h: add unit in max_dram_speed ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63735/comment/fab477c7_a11b500f PS2, Line 7: add unit in max_dram_speed suggestion: `Rename max_dram_speed to include units` -- To view, visit https://review.coreboot.org/c/coreboot/+/63735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83c780440613050c0202f95d5f64991b61d9c280 Gerrit-Change-Number: 63735 Gerrit-PatchSet: 2 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Wed, 20 Apr 2022 18:33:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl/chip.h: add unit in max_dram_speed
by Tim Wawrzynczak (Code Review) 20 Apr '22

20 Apr '22

Attention is currently required from: Paul Menzel, Scott Chao. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63735 ) Change subject: soc/intel/adl/chip.h: add unit in max_dram_speed ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS2: Thanks Scott 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/63735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83c780440613050c0202f95d5f64991b61d9c280 Gerrit-Change-Number: 63735 Gerrit-PatchSet: 2 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Wed, 20 Apr 2022 18:32:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2022