coreboot-gerrit April 2022

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Change in coreboot[master]: tpm: Refactor TPM Kconfig dimensions
by Yu-Ping Wu (Code Review) 21 Apr '22

21 Apr '22

Attention is currently required from: Stefan Ott, Felix Singer, Patrick Rudolph, Jonathan Zhang, Nick Vaccaro, Arthur Heymans, Andrey Petrov, Piotr Król, Jes Klinke, Nico Huber, Sean Rhodes, Michał Żygowski, Johnny Lin, Christian Walter, Werner Zeh, Alexander Couzens, Tim Chu, Frans Hendriks, Tristan Corrick, Jeremy Soller, Julius Werner, Angel Pons, Michael Niewöhner, Tim Crawford, Maxim Polyakov, Tim Wawrzynczak. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63424 ) Change subject: tpm: Refactor TPM Kconfig dimensions ...................................................................... Patch Set 20: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Gerrit-Change-Number: 63424 Gerrit-PatchSet: 20 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Jes Klinke <jbk(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 21 Apr 2022 01:27:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/64bit: Generate static page tables from an assembly file
by Julius Werner (Code Review) 21 Apr '22

21 Apr '22

Attention is currently required from: Raul Rangel, Patrick Rudolph, Arthur Heymans. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63725 ) Change subject: cpu/x86/64bit: Generate static page tables from an assembly file ...................................................................... Patch Set 3: (2 comments) File src/cpu/x86/64bit/Makefile.inc: https://review.coreboot.org/c/coreboot/+/63725/comment/d4fbcdee_72f8c149 PS3, Line 4: -ffreestanding -nostdlib -nostdinc Any reason you can't just reuse `$(CPPFLAGS_ramstage) $(CFLAGS_ramstage)` here? (Also, shouldn't it be bootblock instead of ramstage?) File src/cpu/x86/64bit/pt.S: https://review.coreboot.org/c/coreboot/+/63725/comment/388672fb_83803e80 PS3, Line 27: .quad _GEN_PAGE(0x200000 * 0) > I was wondering if there was a recursion limit. Thanks for trying. I think it's fine as is. Maybe something like this could work: .rept 2048 .quad _GEN_PAGE(0x200000 * (. - PDE_tables) / 8) .endr -- To view, visit https://review.coreboot.org/c/coreboot/+/63725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1e31b701a2584268c85d327bf139953213899e3 Gerrit-Change-Number: 63725 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 21 Apr 2022 01:27:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Support x86 payload loaded via Linux Boot Protocol
by Julius Werner (Code Review) 21 Apr '22

21 Apr '22

Attention is currently required from: Nico Huber. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63748 ) Change subject: libpayload: Support x86 payload loaded via Linux Boot Protocol ...................................................................... Patch Set 1: (2 comments) File payloads/libpayload/arch/x86/head.S: https://review.coreboot.org/c/coreboot/+/63748/comment/75dbb433_c05585f6 PS1, Line 86: jne 1f (Note that as far as I can tell, this hasn't worked in a long time, maybe ever(?)... so we always go into the 1f path here.) https://review.coreboot.org/c/coreboot/+/63748/comment/43d31619_128ab634 PS1, Line 105: esi Where does %esi come from? Is the caller supposed to set it? That would be a problem for callers that don't follow this convention, obviously... (might be random value that points into invalid memory, generating a fault). -- To view, visit https://review.coreboot.org/c/coreboot/+/63748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief6bca8534d07458b9c5a315f297cb62d727917f Gerrit-Change-Number: 63748 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 21 Apr 2022 01:01:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/cbmem: add an option to append timestamp
by Julius Werner (Code Review) 21 Apr '22

21 Apr '22

Attention is currently required from: Mattias Nissler, Paul Menzel. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62639 ) Change subject: util/cbmem: add an option to append timestamp ...................................................................... Patch Set 3: (5 comments) File util/cbmem/cbmem.c: https://review.coreboot.org/c/coreboot/+/62639/comment/f09de891_f391145e PS2, Line 546: return __rdtsc(); > Thanks for calling this out, very good point. […] That should do it for all x86 platforms that use the TSC, yeah. Technically there's nothing preventing x86 platforms from using other time sources (e.g. see CONFIG_LAPIC_MONOTONIC_TIMER). I guess that might not be a problem in practice for the platforms we care about. Arm is still going to be a problem eventually, though. It would be good if we could also converge on all platforms using the architectural timer there. We're already doing that for Qualcomm, the MediaTek folks are still using a custom timer right now, I'll ask them if they can change that. File util/cbmem/cbmem.c: https://review.coreboot.org/c/coreboot/+/62639/comment/640ffb44_9ce6bc60 PS3, Line 32: #if defined(__x86_64__) Can we make this (defined(__i386__) || defined(__x86_64__) ? Chrome OS doesn't use 32-bit x86 userspace anymore, but some other coreboot users still might. https://review.coreboot.org/c/coreboot/+/62639/comment/41522f1f_07ff6041 PS3, Line 467: return tsc_freq_khz / 1000; I'm not sure this is correct, tbh. This code is ancient and from before my time, so I don't really know on which platforms we would even expect the frequency entry to be missing from the table... but for those where it does, the TSC frequency may not necessarily be the right answer. coreboot doesn't always use the TSC for timestamps (especially on older platforms). So either we have to go hunting for someone who still remembers why this code path is here, or maybe just avoid touching it for now. https://review.coreboot.org/c/coreboot/+/62639/comment/e2121a28_d07b748b PS3, Line 557: #if defined(__x86_64__) here too https://review.coreboot.org/c/coreboot/+/62639/comment/9ba7c3ad_5affe9d3 PS3, Line 583: if (!strcmp(timestamp_ids[i].name, name)) How do you expect this to be used... cbmem -a "starting to load romstage" ? That seems impractical. We recently added another field `enum_name` (see CB:62709... because `name` is really more of a `description`). I think using that would make more sense here, e.g. cbmem -a TS_COPYROM_START -- To view, visit https://review.coreboot.org/c/coreboot/+/62639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic99e5a11d8cc3f9fffae8eaf2787652105cf4842 Gerrit-Change-Number: 62639 Gerrit-PatchSet: 3 Gerrit-Owner: Mattias Nissler <mnissler(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mattias Nissler <mnissler(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 21 Apr 2022 00:41:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mattias Nissler <mnissler(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add Raptor Lake device IDs
by Jérémy Compostella (Code Review) 21 Apr '22

21 Apr '22

Attention is currently required from: Bora Guvendik, Anil Kumar K, Subrata Banik, Tim Wawrzynczak. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63750 ) Change subject: soc/intel/common: Add Raptor Lake device IDs ...................................................................... Patch Set 1: (10 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63750/comment/974282cc_c9eeddbc PS1, Line 9: Add Raptor Lake specific CPU, System Agent, PCH, The line break is unnecessary as the line length is 64 characters. Regarding the references I would suggest something like: References: - RaptorLake External Design Specification Volume 1 (640555) - 600/700 Series PCH External Design Specification Volume 1 (626817) Patchset: PS1: See comments inline. File src/include/cpu/intel/cpu_ids.h: https://review.coreboot.org/c/coreboot/+/63750/comment/733469bd_4a48f461 PS1, Line 62: #define CPUID_RAPTORLAKE_J0 0xb06a2 According the EDS section 15.0, there are two SKUs (P and S) with two different CPUIDs. Shouldn't we create CPUID_RAPTORLAKE_P_J0 and CPUID_RAPTORLAKE_S_J0 ? Or at least name it CPUID_RAPTORLAKE_P_J0 ? Also, Are we already at J stepping ? File src/include/device/pci_ids.h: https://review.coreboot.org/c/coreboot/+/63750/comment/05f52443_0a497d1d PS1, Line 3079: #define PCI_DID_INTEL_RPL_P_ESPI_1 0x519d Where does this second eSPI MC comes from ? I don't find it in the PCH EDS. https://review.coreboot.org/c/coreboot/+/63750/comment/c2585f9c_ac9ee241 PS1, Line 4149: #define PCI_DID_INTEL_RPL_TCSS_XHCI 0xa71e Where is it defined? I could not find it. https://review.coreboot.org/c/coreboot/+/63750/comment/fa79ac98_04a38a54 PS1, Line 4350: #define PCI_DID_INTEL_RPL_TBT_RP0 0xa76e Where are they defined? I could not find them. https://review.coreboot.org/c/coreboot/+/63750/comment/3effaf65_14bbf106 PS1, Line 4394: #define PCI_DID_INTEL_RPL_IPU 0xa75d Where is it defined? I could not find it. File src/soc/intel/alderlake/bootblock/report_platform.c: https://review.coreboot.org/c/coreboot/+/63750/comment/9d616722_3b9a9180 PS1, Line 32: { CPUID_RAPTORLAKE_J0, "Raptorlake Platform" }, CPUID_RAPTORLAKE_J0 is actually the Raptor P cpuid. File src/soc/intel/alderlake/cpu.c: https://review.coreboot.org/c/coreboot/+/63750/comment/c4d4bb79_a46403ff PS1, Line 262: adl_p_mch_ids should be rpl_p_mch_ids right ? Also this pattern is repeating over and over, it may be time to introduce a function or a macro? File src/soc/intel/common/block/dtt/dtt.c: https://review.coreboot.org/c/coreboot/+/63750/comment/9a375209_5a2aef61 PS1, Line 8: PCI_DID_INTEL_RPL_DTT, Is there any reason why it is being added at the beginning ? -- To view, visit https://review.coreboot.org/c/coreboot/+/63750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39e655dec2314a672ea63ba90d8bb3fc53bf77ba Gerrit-Change-Number: 63750 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 21 Apr 2022 00:31:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl/chip.h: Rename max_dram_speed to include units
by Scott Chao (Code Review) 21 Apr '22

21 Apr '22

Attention is currently required from: Paul Menzel. Scott Chao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63735 ) Change subject: soc/intel/adl/chip.h: Rename max_dram_speed to include units ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63735/comment/cc491fce_a9f34035 PS2, Line 7: add unit in max_dram_speed > suggestion: […] Done https://review.coreboot.org/c/coreboot/+/63735/comment/3c9fff80_605eddaf PS2, Line 9: on > to Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83c780440613050c0202f95d5f64991b61d9c280 Gerrit-Change-Number: 63735 Gerrit-PatchSet: 3 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 21 Apr 2022 00:10:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl/chip.h: Rename max_dram_speed to include units
by Scott Chao (Code Review) 21 Apr '22

21 Apr '22

Attention is currently required from: Scott Chao. Hello build bot (Jenkins), Paul Menzel, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63735 to look at the new patch set (#3). Change subject: soc/intel/adl/chip.h: Rename max_dram_speed to include units ...................................................................... soc/intel/adl/chip.h: Rename max_dram_speed to include units The unit of dram speed is MT/s so append it on variable name. BUG=b:229549930 BRANCH=none TEST=build coreboot without error Signed-off-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Change-Id: I83c780440613050c0202f95d5f64991b61d9c280 --- M src/mainboard/google/brya/variants/crota/overridetree.cb M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/primus4es/overridetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/romstage/fsp_params.c 5 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/63735/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83c780440613050c0202f95d5f64991b61d9c280 Gerrit-Change-Number: 63735 Gerrit-PatchSet: 3 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: ec/google/chromeec: allow custom command timeout
by Karthik Ramasubramanian (Code Review) 21 Apr '22

21 Apr '22

Attention is currently required from: Raul Rangel, Peter Marheine. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63733 ) Change subject: ec/google/chromeec: allow custom command timeout ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: For completion, this should also update ec_spi.c and ec_i2c.c if we have to support increased timeout. Before that, as Tim mentioned in the bug please check with EC vendor regarding why we need the increased timeout. -- To view, visit https://review.coreboot.org/c/coreboot/+/63733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55d36479e680c34a8bff65776e7e295e94291342 Gerrit-Change-Number: 63733 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Wed, 20 Apr 2022 23:29:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: tpm: Refactor TPM Kconfig dimensions
by Jes Klinke (Code Review) 21 Apr '22

21 Apr '22

Attention is currently required from: Stefan Ott, Felix Singer, Patrick Rudolph, Jonathan Zhang, Nick Vaccaro, Arthur Heymans, Andrey Petrov, Piotr Król, Nico Huber, Sean Rhodes, Michał Żygowski, Johnny Lin, Christian Walter, Werner Zeh, Alexander Couzens, Yu-Ping Wu, Tim Chu, Frans Hendriks, Tristan Corrick, Jeremy Soller, Julius Werner, Angel Pons, Michael Niewöhner, Tim Crawford, Maxim Polyakov, Tim Wawrzynczak. Hello Felix Singer, Stefan Ott, build bot (Jenkins), Patrick Rudolph, Jonathan Zhang, Nick Vaccaro, Arthur Heymans, Andrey Petrov, Piotr Król, Sean Rhodes, Nico Huber, Michał Żygowski, Johnny Lin, Christian Walter, siemens-bot, Werner Zeh, Alexander Couzens, Yu-Ping Wu, Tim Chu, Frans Hendriks, Tristan Corrick, Jeremy Soller, Angel Pons, Julius Werner, Michael Niewöhner, Erik van den Bogaert, Tim Crawford, Maxim Polyakov, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63424 to look at the new patch set (#20). Change subject: tpm: Refactor TPM Kconfig dimensions ...................................................................... tpm: Refactor TPM Kconfig dimensions Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk(a)chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e --- M Documentation/getting_started/kconfig.md M src/drivers/crb/Kconfig M src/drivers/crb/Makefile.inc M src/drivers/i2c/tpm/Kconfig M src/drivers/i2c/tpm/Makefile.inc M src/drivers/pc80/tpm/Kconfig M src/drivers/pc80/tpm/Makefile.inc M src/drivers/spi/tpm/Kconfig M src/drivers/spi/tpm/Makefile.inc M src/drivers/spi/tpm/tpm.c M src/drivers/tpm/Makefile.inc M src/mainboard/acer/aspire_vn7_572g/Kconfig M src/mainboard/asrock/b85m_pro4/Kconfig M src/mainboard/asrock/h110m/Kconfig M src/mainboard/asus/am1i-a/Kconfig M src/mainboard/asus/h61-series/Kconfig.name M src/mainboard/asus/p8x7x-series/Kconfig.name M src/mainboard/clevo/cml-u/Kconfig M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/clevo/tgl-u/Kconfig M src/mainboard/dell/snb_ivb_workstations/Kconfig M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/facebook/fbg1701/Kconfig M src/mainboard/facebook/monolith/Kconfig M src/mainboard/foxconn/g41s-k/Kconfig M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig M src/mainboard/google/asurada/Kconfig M src/mainboard/google/auron/Kconfig M src/mainboard/google/beltino/Kconfig M src/mainboard/google/brya/Kconfig M src/mainboard/google/butterfly/Kconfig M src/mainboard/google/cherry/Kconfig M src/mainboard/google/corsola/Kconfig M src/mainboard/google/cyan/Kconfig M src/mainboard/google/daisy/Kconfig M src/mainboard/google/dedede/Kconfig M src/mainboard/google/deltaur/Kconfig M src/mainboard/google/drallion/Kconfig M src/mainboard/google/eve/Kconfig M src/mainboard/google/fizz/Kconfig M src/mainboard/google/foster/Kconfig M src/mainboard/google/gale/Kconfig M src/mainboard/google/glados/Kconfig M src/mainboard/google/gru/Kconfig M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/hatch/Kconfig M src/mainboard/google/herobrine/Kconfig M src/mainboard/google/herobrine/bootblock.c M src/mainboard/google/jecht/Kconfig M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/kukui/Kconfig M src/mainboard/google/link/Kconfig M src/mainboard/google/nyan_big/Kconfig M src/mainboard/google/nyan_blaze/Kconfig M src/mainboard/google/oak/Kconfig M src/mainboard/google/octopus/Kconfig M src/mainboard/google/parrot/Kconfig M src/mainboard/google/peach_pit/Kconfig M src/mainboard/google/poppy/Kconfig M src/mainboard/google/rambi/Kconfig M src/mainboard/google/reef/Kconfig M src/mainboard/google/sarien/Kconfig M src/mainboard/google/skyrim/Kconfig M src/mainboard/google/slippy/Kconfig M src/mainboard/google/smaug/Kconfig M src/mainboard/google/storm/Kconfig M src/mainboard/google/stout/Kconfig M src/mainboard/google/trogdor/Kconfig M src/mainboard/google/veyron/Kconfig M src/mainboard/google/veyron_mickey/Kconfig M src/mainboard/google/veyron_rialto/Kconfig M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/mainboard.c M src/mainboard/google/volteer/variants/chronicler/overridetree.cb M src/mainboard/google/volteer/variants/volteer2/overridetree.cb M src/mainboard/google/volteer/variants/volteer2/variant.c M src/mainboard/google/zork/Kconfig M src/mainboard/hp/compaq_8200_elite_sff/Kconfig M src/mainboard/hp/folio_9480m/Kconfig M src/mainboard/hp/snb_ivb_laptops/Kconfig M src/mainboard/hp/z220_series/Kconfig M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/baskingridge/Kconfig M src/mainboard/intel/coffeelake_rvp/Kconfig M src/mainboard/intel/galileo/Kconfig M src/mainboard/intel/glkrvp/Kconfig M src/mainboard/intel/kblrvp/Kconfig M src/mainboard/intel/kunimitsu/Kconfig M src/mainboard/intel/shadowmountain/Kconfig M src/mainboard/intel/strago/Kconfig M src/mainboard/intel/tglrvp/Kconfig M src/mainboard/intel/wtm2/Kconfig M src/mainboard/kontron/bsl6/Kconfig M src/mainboard/kontron/mal10/Kconfig M src/mainboard/lenovo/s230u/Kconfig M src/mainboard/lenovo/t410/Kconfig M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420s/Kconfig M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t440p/Kconfig M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t530/Kconfig M src/mainboard/lenovo/w541/Kconfig M src/mainboard/lenovo/x131e/Kconfig M src/mainboard/lenovo/x1_carbon_gen1/Kconfig M src/mainboard/lenovo/x201/Kconfig M src/mainboard/lenovo/x220/Kconfig M src/mainboard/lenovo/x230/Kconfig M src/mainboard/libretrend/lt1000/Kconfig M src/mainboard/ocp/deltalake/Kconfig M src/mainboard/opencellular/elgon/Kconfig M src/mainboard/pcengines/apu1/Kconfig M src/mainboard/pcengines/apu2/Kconfig M src/mainboard/prodrive/hermes/Kconfig M src/mainboard/protectli/vault_kbl/Kconfig M src/mainboard/purism/librem_cnl/Kconfig.name M src/mainboard/purism/librem_skl/Kconfig M src/mainboard/razer/blade_stealth_kbl/Kconfig M src/mainboard/samsung/lumpy/Kconfig M src/mainboard/samsung/stumpy/Kconfig M src/mainboard/siemens/chili/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig M src/mainboard/siemens/mc_ehl/Kconfig M src/mainboard/starlabs/labtop/Kconfig M src/mainboard/starlabs/lite/Kconfig M src/mainboard/supermicro/x11-lga1151-series/Kconfig M src/mainboard/supermicro/x9sae/Kconfig M src/mainboard/system76/addw1/Kconfig M src/mainboard/system76/bonw14/Kconfig M src/mainboard/system76/cml-u/Kconfig M src/mainboard/system76/darp7/Kconfig M src/mainboard/system76/galp5/Kconfig M src/mainboard/system76/gaze15/Kconfig M src/mainboard/system76/gaze16/Kconfig M src/mainboard/system76/kbl-u/Kconfig M src/mainboard/system76/lemp10/Kconfig M src/mainboard/system76/lemp9/Kconfig M src/mainboard/system76/oryp5/Kconfig M src/mainboard/system76/oryp6/Kconfig M src/mainboard/system76/oryp8/Kconfig M src/mainboard/system76/whl-u/Kconfig M src/mainboard/up/squared/Kconfig M src/security/tpm/Kconfig M src/security/tpm/Makefile.inc M src/security/tpm/tss/vendor/cr50/Kconfig M src/security/vboot/secdata_mock.c M src/security/vboot/secdata_tpm.c M src/security/vboot/vboot_logic.c M src/soc/intel/apollolake/Kconfig M src/soc/intel/common/Makefile.inc M src/soc/intel/skylake/acpi/systemagent.asl M src/soc/intel/tigerlake/Kconfig M src/vendorcode/google/chromeos/Kconfig M src/vendorcode/google/chromeos/Makefile.inc M src/vendorcode/google/chromeos/cse_board_reset.c 159 files changed, 260 insertions(+), 289 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/63424/20 -- To view, visit https://review.coreboot.org/c/coreboot/+/63424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Gerrit-Change-Number: 63424 Gerrit-PatchSet: 20 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> 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Change in coreboot[master]: soc/intel/jasperlake: CNVi: Enable fewer wakeups to reduce SoC power ...
by Karthik Ramasubramanian (Code Review) 21 Apr '22

21 Apr '22

Attention is currently required from: Jamie Chen, Tim Wawrzynczak. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63675 ) Change subject: soc/intel/jasperlake: CNVi: Enable fewer wakeups to reduce SoC power consumption ...................................................................... Patch Set 5: (3 comments) Patchset: PS5: Sorry for chiming in late. File src/soc/intel/jasperlake/chip.h: https://review.coreboot.org/c/coreboot/+/63675/comment/66230eb9_87e5dca2 PS5, Line 428: * Setting this on a system that supports S0i3 (set xtalsdqdis [Bit 22] in : * cppmvric1 register to 0) will break CNVI timing. Should we have to assert xtalsdqdis bit is not set when this bit is set? File src/soc/intel/jasperlake/finalize.c: https://review.coreboot.org/c/coreboot/+/63675/comment/8258b873_63e50c57 PS5, Line 63: if (config->cnvi_reduce_s0ix_pwr_usage) { Also should we have to ensure that CNVI device is enabled in the devicetree. What is the impact of setting this on boards that use discrete WiFi? -- To view, visit https://review.coreboot.org/c/coreboot/+/63675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56439a406547e2ee1e47d34be14ecc9a8df04693 Gerrit-Change-Number: 63675 Gerrit-PatchSet: 5 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Wed, 20 Apr 2022 22:58:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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