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Change subject: soc/intel/jasperlake: CNVi: Enable fewer wakeups to reduce SoC power consumption
......................................................................
Patch Set 5:
(2 comments)
File src/soc/intel/jasperlake/chip.h:
https://review.coreboot.org/c/coreboot/+/63675/comment/c544e271_dcb11447
PS5, Line 428: * Setting this on a system that supports S0i3 (set xtalsdqdis [Bit 22] in
: * cppmvric1 register to 0) will break CNVI timing.
> Should we have to assert xtalsdqdis bit is not set when this bit is set?
The xtalsdqdis bit can be set or clear by ASL code or OS code. That's why I add comment here to warning developer instead of adding statement to check if xtalsdqis bit is 0.
File src/soc/intel/jasperlake/finalize.c:
https://review.coreboot.org/c/coreboot/+/63675/comment/38113da8_fab4a710
PS5, Line 63: if (config->cnvi_reduce_s0ix_pwr_usage) {
> Also should we have to ensure that CNVI device is enabled in the devicetree. […]
This is only for system with CNVi module to work around and keeping this enabled will not impact the system with discrete WIFI.
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Change subject: intel/common/../systemagent: Add sa_get_mchbar_base api
......................................................................
Patch Set 11:
(2 comments)
File src/soc/intel/common/block/systemagent/systemagent_early.c:
https://review.coreboot.org/c/coreboot/+/63615/comment/ecbe7bd9_8becf497
PS11, Line 89: if(mchbar_lo & 0x1)
one space between if and brace ?
https://review.coreboot.org/c/coreboot/+/63615/comment/d46fc664_54b7b189
PS11, Line 94: if(mchbar_base == 0) {
one space between if and brace ?
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Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63722 )
Change subject: mb/google/nipperkin: Fix WLAN to GEN2 speed
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/guybrush/variants/nipperkin/variant.c:
https://review.coreboot.org/c/coreboot/+/63722/comment/00941ff3_604863d5
PS4, Line 10: /* Disable PSPP to avoid S0ix hangs - b/228830362 */
: memset(dxio_descriptors[WLAN].port_params, 0,
: sizeof(dxio_descriptors[WLAN].port_params));
> Hi Rob, […]
My understanding is PSPP is on but link speed is limited to a max of gen2 speeds. Link speed may go to gen1 on DC since PSPP policy is balanced. AMD may correct me.
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Change subject: intel/common/../systemagent: Add sa_get_mchbar_base api
......................................................................
Patch Set 10:
(2 comments)
File src/soc/intel/common/block/systemagent/systemagent_early.c:
https://review.coreboot.org/c/coreboot/+/63615/comment/72ba31c7_44b34ee2
PS8, Line 89: if (mchbar_lo & 0x1)
> what if mchbar_lo and hi value is zero and BAR enable bit is set? we would run into the problem isn' […]
Done
https://review.coreboot.org/c/coreboot/+/63615/comment/630639d3_ddba776b
PS8, Line 92:
> tab ?
Done
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Change subject: mb/google/guybrush/var/dewatt: Override SPI fast speed
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63753/comment/d8e93527_9bd17601
PS1, Line 9: 100 MHz SPI fast speed can be
: enabled for SPI ROM.
Awesome!
File src/mainboard/google/guybrush/Kconfig:
https://review.coreboot.org/c/coreboot/+/63753/comment/c3b2526b_1402398e
PS1, Line 140: default 0x3 if BOARD_GOOGLE_DEWATT
Nit: Could we get a comment like the lines above saying what the speed for '3' is?
Really it could go on all of these, but if you could do it for dewatt, that'd be a start.
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Kenneth Chan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63685 )
Change subject: mb/google/guybrush/var/dewatt: Override SPI fast speed
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/guybrush/Kconfig:
https://review.coreboot.org/c/coreboot/+/63685/comment/66582850_0cef1e5d
PS2, Line 143: 0x2
> I believe it should be 3 for Dewatt. Sorry for the delayed response.
Thank your minding, re-upload CL with board id 0x03:
https://review.coreboot.org/c/coreboot/+/63753
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Martin L Roth has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/63754 )
Change subject: RFC: Kconfig - show boards supported on 4.11 branch (POC)
......................................................................
RFC: Kconfig - show boards supported on 4.11 branch (POC)
This patch is a proof of concept for the idea of showing boards that are
no longer supported on the master branch. They can be selected in
Kconfig, but the user is told 3 different ways which branch the board
is supported in.
1) When selecting the mainboard, it's in the mainboard name.
2) When exiting from Kconfig, the main menu is gone, and a note saying
that the user needs to check out a branch to build that board.
3) When make is run after saving the .config file, it halts, telling the
user what needs to be checked out.
As a proof of concept, I've only implemented a few boards from the 4.11
branch, but the concept is similar for any board on any branch.
We could check out the branch for the user, but there was debate in the
leadership meeting about whether that would be expected or not, so it's
not implemented in this patch, but it would be simple to add a script
that would check the branch out for you.
There were also concerns about the Kconfig that was generated not working
correctly in the branch. That should be fixed with this change as the
saved .config is very minimal. By excluding the rest of the Kconfig if
a branch build is selected, the resulting Kconfig basically just has the
board vendor and defaults, thus acts similar to a defconfig.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: I5fe1c508e97b52a6b70b33107c6e17cc7d7faeb2
---
M Makefile
M src/Kconfig
M src/mainboard/Kconfig
A src/mainboard/adi/Kconfig
A src/mainboard/adi/Kconfig.branch
A src/mainboard/adi/Kconfig.name
A src/mainboard/advansus/Kconfig
A src/mainboard/advansus/Kconfig.branch
A src/mainboard/advansus/Kconfig.name
M src/mainboard/amd/Kconfig
A src/mainboard/amd/Kconfig.branch
11 files changed, 144 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/63754/2
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