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Hello build bot (Jenkins), Kangheui Won, Tim Wawrzynczak, Nick Vaccaro,
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Change subject: mb/google/brya/var/craask: Generate SPD ID for supported memory part
......................................................................
mb/google/brya/var/craask: Generate SPD ID for supported memory part
Add supported memory parts in mem_parts_used.txt, and generate SPD id
for this part.
MT62F1G32D4DR-031 WT:B
MT62F512M32D2DR-031 WT:B
BUG=229938024
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com>
Change-Id: I183b74e66786c378cc227ee1e53ea422986b672a
---
M src/mainboard/google/brya/variants/craask/memory/Makefile.inc
M src/mainboard/google/brya/variants/craask/memory/dram_id.generated.txt
M src/mainboard/google/brya/variants/craask/memory/mem_parts_used.txt
3 files changed, 14 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/63738/4
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Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63680 )
Change subject: lib: Add LPDDR5 DRAM type
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
IMO, from Meera's CL https://review.coreboot.org/c/coreboot/+/52731, looks like DDR5 is 1024 byte. This make me wonder is LPDDR5 full compatible to DDR5 or not.
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Change subject: lib: Add LPDDR5 DRAM type
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> Any document you refer?
We boot LPDDR5 system and it showed "Defaulting to using DDR4 params". So I add this CL.
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Change subject: lib: Add LPDDR5 DRAM type
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Any document you refer?
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Change subject: lib: Add LPDDR5 DRAM type
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/intel/jasperlake: Revert CdClock setting
......................................................................
Patch Set 3: Code-Review+1
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Hello build bot (Jenkins), Raul Rangel, Eric Lai, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/skyrim: Configure SD_AUX_RESET_L signal
......................................................................
mb/google/skyrim: Configure SD_AUX_RESET_L signal
Set native function (SD_AUX_RESET_L), and drive it low, then high.
BUG=b:229181624
TEST=Build and boot to OS in Skyrim. Ensure that the SD Controller
and SD Card are enumerated fine.
02:00.0 SD Host controller: Genesys Logic, Inc GL9750 (rev 01)
Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com>
Change-Id: I03d88d90acc03cdebcb1e83ed2e799dda8b5b735
---
M src/mainboard/google/skyrim/variants/baseboard/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/63739/7
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Change subject: mb/google/skyrim: Configure SD_AUX_RESET_L signal
......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/google/skyrim/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/63739/comment/fa9b7275_c5a25d0e
PS5, Line 189: /* SD_AUX_RESET_L */
: PAD_GPO(GPIO_27, LOW),
> I think this pin will always get reset, so no need to add it here.
Done
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#6).
Change subject: mb/google/skyrim: Configure SD_AUX_RESET_L signal
......................................................................
mb/google/skyrim: Configure SD_AUX_RESET_L signal
Set native function (PCIE_RST_L), and drive it low, then high.
BUG=b:229181624
TEST=Build and boot to OS in Skyrim. Ensure that the SD Controller
and SD Card are enumerated fine.
02:00.0 SD Host controller: Genesys Logic, Inc GL9750 (rev 01)
Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com>
Change-Id: I03d88d90acc03cdebcb1e83ed2e799dda8b5b735
---
M src/mainboard/google/skyrim/variants/baseboard/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/63739/6
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