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Change subject: mb/google/skyrim: Configure SD card reader power sequence
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/skyrim/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/63739/comment/6b3ebd0d_228237f8
PS5, Line 201: PAD_GPO
> Can you try the following: `PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH),` also update it in the ramstage lis […]
I try modify to `PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH),` in ramstage and SD Card are enumerated fine.
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Change subject: lib: Add LPDDR5 DRAM type
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Hi Subrata, can you help to review this CL? Thanks.
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Change subject: mb/google/brya/var/vell: Fix camera LED flicker problem
......................................................................
Patch Set 7: Code-Review+1
(4 comments)
This change is ready for review.
Commit Message:
https://review.coreboot.org/c/coreboot/+/63441/comment/e070f978_e7086a31
PS5, Line 10: ,
> .
Done
https://review.coreboot.org/c/coreboot/+/63441/comment/033cd303_9134864b
PS5, Line 13: and prevent camera LED flicker
> preventing camera LED flicker.
Done
https://review.coreboot.org/c/coreboot/+/63441/comment/bda28e34_b3775cc2
PS5, Line 16: flicker
> flickers
Done
File src/mainboard/google/brya/variants/vell/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/63441/comment/33728b69_5e0744fd
PS5, Line 314: register "on_seq.ops_cnt" = "4"
: register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
: register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
: register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 5)"
: register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
:
: #_OFF
: register "off_seq.ops_cnt" = "3"
: register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
: register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
: register "off_seq.ops[2]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
:
: device i2c 36 on end
: end
: chip drivers/intel/mipi_camera
: register "acpi_hid" = "ACPI_DT_NAMESPACE_HID"
> You do not mention these changes in the commit message.
Done
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Change subject: soc/intel/jasperlake: Revert CdClock setting
......................................................................
Set Ready For Review
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Change subject: soc/intel/jasperlake: Revert CdClock setting
......................................................................
Patch Set 1:
This change is ready for review.
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Change subject: soc/intel/alderlake/retimer.c: Do not access TCSS devices on ADL-S
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
If you don't select CONFIG_DRIVERS_INTEL_USB4_RETIMER, this won't be called.
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Change subject: console/Kconfig: Reverse NO_POST and depend on ARCH_X86
......................................................................
Patch Set 2:
(1 comment)
File src/console/Kconfig:
https://review.coreboot.org/c/coreboot/+/63678/comment/fd9b9fd3_a864e95b
PS2, Line 418: depends on ARCH_X86
Well there are post_code() calls under device/ and lib/ and implementation separates the need for <arch/io.h>. So CONSOLE_POST would already work on ARM?
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Change subject: Kconfig: Hide stage cache selection on !HAVE_ACPI_RESUME
......................................................................
Patch Set 1:
(1 comment)
File src/Kconfig:
https://review.coreboot.org/c/coreboot/+/63677/comment/121b8e5c_9a774cda
PS1, Line 331: depends on HAVE_ACPI_RESUME
With this HAVE_ACPI_RESUME=n implies NO_STAGE_CACHE=n, and resume_from_stage_cache() will actually call romstage_handoff_is_resume().
Not a big deal, maybe you want to add !CONFIG(HAVE_ACPI_RESUME) there?
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Hello build bot (Jenkins), Martin L Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61954
to look at the new patch set (#3).
Change subject: payloads/coreinfo/coreboot_module.c: Remove 'break' after 'return'
......................................................................
payloads/coreinfo/coreboot_module.c: Remove 'break' after 'return'
Change-Id: Icb60115349ef7c4c35635021784138d45c5a8872
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M payloads/coreinfo/coreboot_module.c
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/61954/3
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