coreboot-gerrit April 2022

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Change in coreboot[master]: mb/google/poppy: Convert 'If (LGreater(STA,0))' to 'If (STA > 0)'
by Martin L Roth (Code Review) 25 Apr '22

25 Apr '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61232 ) Change subject: mb/google/poppy: Convert 'If (LGreater(STA,0))' to 'If (STA > 0)' ...................................................................... mb/google/poppy: Convert 'If (LGreater(STA,0))' to 'If (STA > 0)' Change-Id: I088e514271b785e59907b0271eb89727ae1e7c05 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61232 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <martinroth(a)google.com> --- M src/mainboard/google/poppy/variants/atlas/include/variant/acpi/cam0.asl 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/cam0.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/cam0.asl index b973200..4809f26 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/cam0.asl +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/cam0.asl @@ -12,7 +12,7 @@ PMOF () } Method (_STA, 0, Serialized) { - If (LGreater(STA,0)) { + If (STA > 0) { Return (0x1) } Else { -- To view, visit https://review.coreboot.org/c/coreboot/+/61232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I088e514271b785e59907b0271eb89727ae1e7c05 Gerrit-Change-Number: 61232 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: payloads/coreinfo/coreboot_module.c: Remove unuseful 'break' after 'r...
by Martin L Roth (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: Elyes Haouas. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61954 ) Change subject: payloads/coreinfo/coreboot_module.c: Remove unuseful 'break' after 'return' ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61954/comment/e41508e8_9dcfbdb4 PS2, Line 7: unuseful Remove "unuseful" to shorten the subject? -- To view, visit https://review.coreboot.org/c/coreboot/+/61954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb60115349ef7c4c35635021784138d45c5a8872 Gerrit-Change-Number: 61954 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 24 Apr 2022 22:27:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/coreinfo: Reformat code
by Martin L Roth (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: Elyes Haouas. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61952 ) Change subject: payloads/coreinfo: Reformat code ...................................................................... Patch Set 2: (1 comment) File payloads/coreinfo/pci_module.c: https://review.coreboot.org/c/coreboot/+/61952/comment/1eafc6f7_317fca97 PS2, Line 227: This change seems unintentional. -- To view, visit https://review.coreboot.org/c/coreboot/+/61952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I575134a4070e08956f8e4dee7677349fd418f2ee Gerrit-Change-Number: 61952 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 24 Apr 2022 22:25:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Create mithrax variant
by Martin L Roth (Code Review) 25 Apr '22

25 Apr '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63776 ) Change subject: mb/google/brya: Create mithrax variant ...................................................................... mb/google/brya: Create mithrax variant Create the mithrax variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:223091246 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_MITHRAX Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: I7c2fa6a74cc8e37397dea7e67e8cfa6506a49bdb Reviewed-on: https://review.coreboot.org/c/coreboot/+/63776 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/mithrax/include/variant/ec.h A src/mainboard/google/brya/variants/mithrax/include/variant/gpio.h A src/mainboard/google/brya/variants/mithrax/memory/Makefile.inc A src/mainboard/google/brya/variants/mithrax/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/mithrax/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/mithrax/overridetree.cb 8 files changed, 45 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 5263323..a064ab3 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -174,6 +174,7 @@ default "Kinox" if BOARD_GOOGLE_KINOX default "Craask" if BOARD_GOOGLE_CRAASK default "Osiris" if BOARD_GOOGLE_OSIRIS + default "Mithrax" if BOARD_GOOGLE_MITHRAX config VARIANT_DIR default "brya0" if BOARD_GOOGLE_BRYA0 @@ -203,6 +204,7 @@ default "kinox" if BOARD_GOOGLE_KINOX default "craask" if BOARD_GOOGLE_CRAASK default "osiris" if BOARD_GOOGLE_OSIRIS + default "mithrax" if BOARD_GOOGLE_MITHRAX config VBOOT select VBOOT_EARLY_EC_SYNC diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 216803f..ae5314c 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -203,3 +203,7 @@ config BOARD_GOOGLE_OSIRIS bool "-> Osiris" select BOARD_GOOGLE_BASEBOARD_BRYA + +config BOARD_GOOGLE_MITHRAX + bool "-> Mithrax" + select BOARD_GOOGLE_BASEBOARD_BRYA diff --git a/src/mainboard/google/brya/variants/mithrax/include/variant/ec.h b/src/mainboard/google/brya/variants/mithrax/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/mithrax/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/mithrax/include/variant/gpio.h b/src/mainboard/google/brya/variants/mithrax/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/mithrax/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/mithrax/memory/Makefile.inc b/src/mainboard/google/brya/variants/mithrax/memory/Makefile.inc new file mode 100644 index 0000000..eace2e4 --- /dev/null +++ b/src/mainboard/google/brya/variants/mithrax/memory/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/brya/variants/mithrax/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/mithrax/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/brya/variants/mithrax/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/brya/variants/mithrax/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/mithrax/memory/mem_parts_used.txt new file mode 100644 index 0000000..9621137 --- /dev/null +++ b/src/mainboard/google/brya/variants/mithrax/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/brya/variants/mithrax/overridetree.cb b/src/mainboard/google/brya/variants/mithrax/overridetree.cb new file mode 100644 index 0000000..4f2c04a --- /dev/null +++ b/src/mainboard/google/brya/variants/mithrax/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/63776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c2fa6a74cc8e37397dea7e67e8cfa6506a49bdb Gerrit-Change-Number: 63776 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Anson Tseng <ansontseng(a)google.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: tpm: Allow separate handling of Google Ti50 TPM
by Martin L Roth (Code Review) 25 Apr '22

25 Apr '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63158 ) Change subject: tpm: Allow separate handling of Google Ti50 TPM ...................................................................... tpm: Allow separate handling of Google Ti50 TPM A new iteration of Google's TPM implementation will advertize a new DID:VID, but otherwise follow the same protocol as the earlier design. This change makes use of Kconfigs TPM_GOOGLE_CR50 and TPM_GOOGLE_TI50 to be able to take slightly different code paths, when e.g. evaluating whether TPM firmware is new enough to support certain features. Change-Id: I1e1f8eb9b94fc2d5689656335dc1135b47880986 Signed-off-by: Jes B. Klinke <jbk(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63158 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/drivers/i2c/tpm/Kconfig M src/drivers/i2c/tpm/cr50.c M src/drivers/spi/tpm/tpm.c M src/drivers/tpm/cr50.c M src/drivers/tpm/cr50.h M src/mainboard/google/brya/Kconfig 6 files changed, 32 insertions(+), 39 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/drivers/i2c/tpm/Kconfig b/src/drivers/i2c/tpm/Kconfig index 8efcbaf..0e7856d 100644 --- a/src/drivers/i2c/tpm/Kconfig +++ b/src/drivers/i2c/tpm/Kconfig @@ -3,15 +3,6 @@ help I2C TPM driver is enabled! -config MAINBOARD_NEEDS_I2C_TI50_WORKAROUND - bool - default n - help - Ti50 FW versions below 0.15 don't support the firmware_version or board_cfg registers, - and trying to access them causes I2C errors. This config will skip accesses to these - registers, and should be selected for boards using Ti50 chips with FW < 0.15. The config - will be removed once all Ti50 stocks are updated to 0.15 or higher. - config DRIVER_TIS_DEFAULT bool depends on I2C_TPM diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index 7eb066d..0130b93 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -36,6 +36,7 @@ #define CR50_TIMEOUT_NOIRQ_MS 20 /* Timeout for TPM ready without IRQ */ #define CR50_TIMEOUT_IRQ_MS 100 /* Timeout for TPM ready with IRQ */ #define CR50_DID_VID 0x00281ae0L +#define TI50_DID_VID 0x504a6666L struct tpm_inf_dev { int bus; @@ -455,7 +456,7 @@ rc = cr50_i2c_read(TPM_DID_VID(0), (uint8_t *)did_vid, 4); /* Exit once DID and VID verified */ - if (!rc && (*did_vid == CR50_DID_VID)) { + if (!rc && (*did_vid == CR50_DID_VID || *did_vid == TI50_DID_VID)) { printk(BIOS_INFO, "done! DID_VID 0x%08x\n", *did_vid); return 0; } @@ -474,7 +475,6 @@ int tpm_vendor_init(struct tpm_chip *chip, unsigned int bus, uint32_t dev_addr) { - struct cr50_firmware_version ver; uint32_t did_vid = 0; if (dev_addr == 0) { @@ -500,12 +500,10 @@ printk(BIOS_DEBUG, "cr50 TPM 2.0 (i2c %u:0x%02x id 0x%x)\n", bus, dev_addr, did_vid >> 16); - /* Ti50 FW version under 0.15 doesn't support board cfg command - TODO: remove this flag after all stocks Ti50 uprev to 0.15 or above */ - if (!CONFIG(MAINBOARD_NEEDS_I2C_TI50_WORKAROUND) && tpm_first_access_this_boot()) { + if (tpm_first_access_this_boot()) { /* This is called for the side-effect of printing the version string. */ - cr50_get_firmware_version(&ver); - cr50_set_board_cfg(); + cr50_get_firmware_version(NULL); + cr50_set_board_cfg(); } chip->is_open = 1; diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index 1462dd9..8625a79 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -419,6 +419,7 @@ /* Device/vendor ID values of the TPM devices this driver supports. */ static const uint32_t supported_did_vids[] = { 0x00281ae0, /* H1 based Cr50 security chip. */ + 0x504a6666, /* H1D3C based Ti50 security chip. */ 0x0000104a /* ST33HTPH2E32 */ }; @@ -496,15 +497,13 @@ printk(BIOS_INFO, "Connected to device vid:did:rid of %4.4x:%4.4x:%2.2x\n", tpm_info.vendor_id, tpm_info.device_id, tpm_info.revision); - /* Do some cr50-specific things here. */ - if (CONFIG(TPM_GOOGLE) && tpm_info.vendor_id == 0x1ae0) { - struct cr50_firmware_version ver; - + /* Do some GSC-specific things here. */ + if (CONFIG(TPM_GOOGLE)) { if (tpm_first_access_this_boot()) { /* This is called for the side-effect of printing the firmware version string */ - cr50_get_firmware_version(&ver); - cr50_set_board_cfg(); + cr50_get_firmware_version(NULL); + cr50_set_board_cfg(); } } return 0; diff --git a/src/drivers/tpm/cr50.c b/src/drivers/tpm/cr50.c index 4ab01fb..22ca3dd 100644 --- a/src/drivers/tpm/cr50.c +++ b/src/drivers/tpm/cr50.c @@ -5,6 +5,9 @@ #include <string.h> #include <types.h> +#define CR50_DID_VID 0x00281ae0L +#define TI50_DID_VID 0x504a6666L + #define CR50_BOARD_CFG_LOCKBIT_MASK 0x80000000U #define CR50_BOARD_CFG_FEATUREBITS_MASK 0x3FFFFFFFU @@ -84,7 +87,7 @@ const enum cb_err ret = tis_vendor_read(get_reg_addr(CR50_BOARD_CFG_REG), &value, sizeof(value)); if (ret != CB_SUCCESS) { - printk(BIOS_INFO, "Error reading from cr50\n"); + printk(BIOS_ERR, "Error reading from Cr50\n"); return 0; } @@ -96,6 +99,11 @@ */ enum cb_err cr50_set_board_cfg(void) { + /* If we get here and we aren't cr50, then we must be ti50 which does + * not currently need to support a board_cfg register. */ + if (!CONFIG(TPM_GOOGLE_CR50)) + return CB_SUCCESS; + struct cr50_firmware_version ver; enum cb_err ret; uint32_t value; @@ -109,7 +117,7 @@ /* Set the CR50_BOARD_CFG register, for e.g. asking cr50 to use longer ready pulses. */ ret = tis_vendor_read(get_reg_addr(CR50_BOARD_CFG_REG), &value, sizeof(value)); if (ret != CB_SUCCESS) { - printk(BIOS_INFO, "Error reading from cr50\n"); + printk(BIOS_ERR, "Error reading from Cr50\n"); return CB_ERR; } @@ -142,19 +150,15 @@ bool cr50_is_long_interrupt_pulse_enabled(void) { - /* - * Ti50 FW versions under 0.15 don't support the board cfg register, - * and all Ti50 versions only support long IRQ pulses. - * TODO: Remove this after all Ti50 stocks uprev to 0.15 or above. - */ - if (CONFIG(MAINBOARD_NEEDS_I2C_TI50_WORKAROUND)) - return true; + if (CONFIG(TPM_GOOGLE_CR50)) + return !!(cr50_get_board_cfg() & CR50_BOARD_CFG_100US_READY_PULSE); - return !!(cr50_get_board_cfg() & CR50_BOARD_CFG_100US_READY_PULSE); + /* Ti50 and future GSCs will support only long interrupt pulses. */ + return true; } static enum cb_err cr50_parse_fw_version(const char *version_str, - struct cr50_firmware_version *ver) + struct cr50_firmware_version *ver) { int epoch, major, minor; @@ -219,6 +223,7 @@ } success: - *version = cr50_firmware_version; + if (version) + *version = cr50_firmware_version; return CB_SUCCESS; } diff --git a/src/drivers/tpm/cr50.h b/src/drivers/tpm/cr50.h index f754e13..b39d744 100644 --- a/src/drivers/tpm/cr50.h +++ b/src/drivers/tpm/cr50.h @@ -5,7 +5,7 @@ #include <types.h> -/* Structure describing the elements of Cr50 firmware version. */ +/* Structure describing the elements of GSC firmware version. */ struct cr50_firmware_version { int epoch; int major; @@ -15,7 +15,7 @@ /* Indicates whether Cr50 ready pulses are guaranteed to be at least 100us. */ bool cr50_is_long_interrupt_pulse_enabled(void); -/* Get the Cr50 firmware version information. */ +/* Get the GSC firmware version information. */ enum cb_err cr50_get_firmware_version(struct cr50_firmware_version *version); /* Set the BOARD_CFG register depending on Cr50 Kconfigs */ diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 1a3cb55..5263323 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -1,7 +1,6 @@ config BOARD_GOOGLE_BRYA_COMMON def_bool n select BOARD_ROMSIZE_KB_32768 - select CR50_USE_LONG_INTERRUPT_PULSES select DRIVERS_GENERIC_ALC1015 select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENERIC_MAX98357A @@ -37,7 +36,6 @@ select SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES if SOC_INTEL_ALDERLAKE_PCH_P select SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE - select TPM_GOOGLE_CR50 config BOARD_GOOGLE_BASEBOARD_BRYA def_bool n @@ -46,6 +44,7 @@ select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_BANSHEE select SOC_INTEL_ALDERLAKE_PCH_P select SYSTEM_TYPE_LAPTOP + select TPM_GOOGLE_CR50 config BOARD_GOOGLE_BASEBOARD_BRASK def_bool n @@ -57,16 +56,17 @@ select RT8168_GET_MAC_FROM_VPD select RT8168_SET_LED_MODE select SOC_INTEL_ALDERLAKE_PCH_P + select TPM_GOOGLE_CR50 config BOARD_GOOGLE_BASEBOARD_NISSA def_bool n select BOARD_GOOGLE_BRYA_COMMON select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS - select MAINBOARD_NEEDS_I2C_TI50_WORKAROUND select MEMORY_SOLDERDOWN select SOC_INTEL_ALDERLAKE_PCH_N select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW select SYSTEM_TYPE_LAPTOP + select TPM_GOOGLE_TI50 if BOARD_GOOGLE_BRYA_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/63158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e1f8eb9b94fc2d5689656335dc1135b47880986 Gerrit-Change-Number: 63158 Gerrit-PatchSet: 18 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jett Rink <jettrink(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: merged

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Change in coreboot[master]: tpm: Allow separate handling of Google Ti50 TPM
by Martin L Roth (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: Jes Klinke, Tim Wawrzynczak, Christian Walter, Angel Pons, Jett Rink. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63158 ) Change subject: tpm: Allow separate handling of Google Ti50 TPM ...................................................................... Patch Set 17: (1 comment) File src/drivers/tpm/cr50.c: https://review.coreboot.org/c/coreboot/+/63158/comment/6ef314bf_e220e5ba PS17, Line 7: : #define CR50_DID_VID 0x00281ae0L : #define TI50_DID_VID 0x504a6666L Nit: Maybe look at moving these to a header file that can be included in both files? -- To view, visit https://review.coreboot.org/c/coreboot/+/63158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e1f8eb9b94fc2d5689656335dc1135b47880986 Gerrit-Change-Number: 63158 Gerrit-PatchSet: 17 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jett Rink <jettrink(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Jes Klinke <jbk(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jett Rink <jettrink(a)google.com> Gerrit-Comment-Date: Sun, 24 Apr 2022 22:09:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: xcompile: Hard-code gcc-12
by Martin L Roth (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: Paul Menzel. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62831 ) Change subject: xcompile: Hard-code gcc-12 ...................................................................... Patch Set 1: (3 comments) Patchset: PS1: I'm not sure if this was supposed to be a private patch, but if it's for submission, we need to qualify the use of gcc-12. File util/xcompile/xcompile: https://review.coreboot.org/c/coreboot/+/62831/comment/a6be97bd_adc2e2f5 PS1, Line 64: gcc-12 I'm not sure that this is what we want here. What about other systems than debian? How about adding a check for gcc-12 instead? if program_exists "${XGCCPATH}/gcc"; then HOSTCC="${XGCCPATH}/gcc" elif program_exists gcc-12; then HOSTCC=gcc-12 elif program_exists gcc; then HOSTCC=gcc elif program_exists cc; then HOSTCC=cc else die "no host compiler found" fi https://review.coreboot.org/c/coreboot/+/62831/comment/6300c114_17a4c3cf PS1, Line 302: NM_${TARCH}:=${GCCPREFIX}gcc-nm-12 Here, let's check for $HOSTCC == gcc-12 before setting this, both here and below. ifeq (\${HOSTCC},gcc-12) NM_${TARCH}:=${GCCPREFIX}gcc-nm-12 AR_${TARCH}:=${GCCPREFIX}gcc-ar-12 else NM_${TARCH}:=${GCCPREFIX}gcc-nm AR_${TARCH}:=${GCCPREFIX}gcc-ar endif -- To view, visit https://review.coreboot.org/c/coreboot/+/62831 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8c38cbe2f76350eda7f36861523a5012a13fc0b Gerrit-Change-Number: 62831 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sun, 24 Apr 2022 22:01:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/pc80/vga: Use write to fix array out of bounds warning
by Martin L Roth (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: Paul Menzel. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62829 ) Change subject: drivers/pc80/vga: Use write to fix array out of bounds warning ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62829/comment/679a5aa4_e6ac4d23 PS1, Line 10: x86_64-linux-gnu-gcc-12 -MMD -Isrc -Isrc/include -Isrc/commonlib/include -Isrc/commonlib/bsd/include -Ibuild -I3rdparty/vboot/firmware/include -include src/include/kconfig.h -include src/include/rules.h -include src/commonlib/bsd/include/commonlib/bsd/compiler.h -I3rdparty -D__BUILD_DIR__=\"build\" -Isrc/arch/x86/include -D__ARCH_x86_32__ -pipe -g -nostdinc -std=gnu11 -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough -Wshadow -Wdate-time -Wtype-limits -Wvla -Wdangling-else -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie -Wno-packed-not-aligned -fconserve-stack -Wnull-dereference -Wreturn-type -Wlogical-op -Wduplicated-cond -Wno-unused-but-set-variable -Werror -Os -Wno-address-of-packed-member -m32 -Wl,-b,elf32-i386 -Wl,-melf_i386 -m32 -fuse-ld=bfd -fno-stack-protector -Wl,--build-id=none -fno-delete-null-pointer-checks -Wlogical-op -march=i686 -mno-mmx -MT build/ramstage/drivers/pc80/vga/vga.o -D__RAMSTAGE__ -c -o build/ramstage/drivers/pc80/vga/vga.o src/drivers/pc80/vga/vga.c Maybe remove this? It doesn't really contribute anything. -- To view, visit https://review.coreboot.org/c/coreboot/+/62829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb60fb4ca08ae39a8628bc2543417819ee9dcbb2 Gerrit-Change-Number: 62829 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sun, 24 Apr 2022 21:44:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: lib/cbfs: Compare addresses instead of arrays
by Martin L Roth (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: Paul Menzel, Julius Werner. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62827 ) Change subject: lib/cbfs: Compare addresses instead of arrays ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Can we just set -Wno-array-compare instead? There's nothing illegal about that expression and as we […] Agreed. -- To view, visit https://review.coreboot.org/c/coreboot/+/62827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69310b0bec166faa40f56a36c6d360065cf6b08a Gerrit-Change-Number: 62827 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Sun, 24 Apr 2022 21:40:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: x86: mmio: Qualify variables as volatile
by Martin L Roth (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: Paul Menzel, Julius Werner. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62828 ) Change subject: x86: mmio: Qualify variables as volatile ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Sounds like GCC just fixed this issue and backported it to gcc-11.3: https://gcc.gnu. […] Done. CB:63807 Well, it's not merged yet, but at least the patch is pushed for testing. -- To view, visit https://review.coreboot.org/c/coreboot/+/62828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2769bb0e365aa9d82d709d3715323819bc9de6e Gerrit-Change-Number: 62828 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Sun, 24 Apr 2022 21:38:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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