coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/octopus/Kconfig: Remove space saving options
by Angel Pons (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49345 ) Change subject: mb/google/octopus/Kconfig: Remove space saving options ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I208211d30cc2805113a16a02cdab957b8c584c92 Gerrit-Change-Number: 49345 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 25 Apr 2022 08:19:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/socket_p: Increase DCACHE_RAM_SIZE
by Angel Pons (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: Arthur Heymans, Alexander Couzens, Patrick Rudolph, Swift Geek (Sebastian Grzywna). Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52942 ) Change subject: cpu/intel/socket_p: Increase DCACHE_RAM_SIZE ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d6f7f9151ecd4c9fbbba4ed033dfda8724b6772 Gerrit-Change-Number: 52942 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Comment-Date: Mon, 25 Apr 2022 08:19:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation/infra/builders.md: Fix markdown inssues
by Angel Pons (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: Felix Singer, Martin L Roth. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63804 ) Change subject: Documentation/infra/builders.md: Fix markdown inssues ...................................................................... Patch Set 1: Code-Review+1 (2 comments) File Documentation/infrastructure/builders.md: https://review.coreboot.org/c/coreboot/+/63804/comment/34d84edc_4b4be035 PS1, Line 52: Gleefulbuilder - 64 thread, 64GiB RAM The leading asterisk is gone, does it matter? https://review.coreboot.org/c/coreboot/+/63804/comment/bb78b23d_507dee5c PS1, Line 52: thread thread*s* -- To view, visit https://review.coreboot.org/c/coreboot/+/63804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82317f51c003b2c23d64c3cbbcecbf9a39d5d509 Gerrit-Change-Number: 63804 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Comment-Date: Mon, 25 Apr 2022 08:03:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/craask: Add GPIO table and Fw_config settings
by Tyler Wang (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63817 to look at the new patch set (#2). Change subject: mb/google/brya/var/craask: Add GPIO table and Fw_config settings ...................................................................... mb/google/brya/var/craask: Add GPIO table and Fw_config settings 1. Fill GPIO table for Craask. 2. Disable LTE-related GPIOs based on fw_config BUG=b:229938024 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Change-Id: I3b85b4b7a68211013f5862d71c8e31ecec41c7b2 --- A src/mainboard/google/brya/variants/craask/Makefile.inc A src/mainboard/google/brya/variants/craask/fw_config.c A src/mainboard/google/brya/variants/craask/gpio.c 3 files changed, 83 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/63817/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b85b4b7a68211013f5862d71c8e31ecec41c7b2 Gerrit-Change-Number: 63817 Gerrit-PatchSet: 2 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lenovo/x230: introduce FHD variant
by Angel Pons (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: Nico Huber, Xue Yao, Paul Menzel, Kilian Neuner, Charles Moyes, Alexander Couzens. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 16: (6 comments) File src/mainboard/lenovo/x230/Kconfig: https://review.coreboot.org/c/coreboot/+/28950/comment/99ded5a4_7b0b9eea PS16, Line 57: default "x230_edp" if BOARD_LENOVO_X230_EDP I wouldn't do this. I'd treat `BOARD_LENOVO_X230_EDP` just like `BOARD_LENOVO_X230` and handle the differences in `INTEL_GMA_VBT_FILE` and Makefile.inc (see my other comments). https://review.coreboot.org/c/coreboot/+/28950/comment/f9cd6e9d_c4738297 PS16, Line 63: default "ThinkPad X230 edp" if BOARD_LENOVO_X230_EDP I wouldn't change this, it's used in the ID section (a rudimentary mechanism for tools to know which board a coreboot image is for). If flashrom detects a mismatch between the flash chip's ID section and the file to flash's ID section, it will complain and bail out. TL;DR: Please use the same name as the regular X230 for compatibility. https://review.coreboot.org/c/coreboot/+/28950/comment/21ee407d_ffbdcef0 PS16, Line 85: config INTEL_GMA_VBT_FILE : string : default "variants/\$(CONFIG_VARIANT_DIR)/data.vbt" if BOARD_LENOVO_X230S || BOARD_LENOVO_X230_EDP : default "variants/x230/data.vbt" if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T Without using the x230_edp variant, this can be simplified to: config INTEL_GMA_VBT_FILE default "variants/x230_edp/data.vbt" if BOARD_LENOVO_X230_EDP File src/mainboard/lenovo/x230/Makefile.inc: https://review.coreboot.org/c/coreboot/+/28950/comment/14cff301_9da58f9f PS16, Line 13: ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads Instead of adding Kconfig options for the other three files, how about handling the special case of X230_EDP directly in the Makefile? ifeq ($(CONFIG_BOARD_LENOVO_X230_EDP),y) ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/x230_edp/gma-mainboard.ads endif else ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads endif File src/mainboard/lenovo/x230/variants/x230_edp/board_info.txt: PS16: Shouldn't be needed File src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads: https://review.coreboot.org/c/coreboot/+/28950/comment/485f8edc_0594e4c9 PS16, Line 2: -- This file is part of the coreboot project. Please remove this line -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 16 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kilian Neuner <cb(a)9-r.net> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aleksei Kharlamov <derlafff(a)ya.ru> Gerrit-CC: Charles Moyes <thechuckster(a)gmail.com> Gerrit-CC: Christian Herzog Gerrit-CC: Holger Levsen <holger(a)layer-acht.org> Gerrit-CC: MartiniMoe Gerrit-CC: Matthias Wiedhalm Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Pavel Kovalenko <su(a)nitrocaster.me> Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Stanislaw Kaminski <stanislaw.kaminski(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-CC: Tomasz Jan Góralczyk Gerrit-CC: Xue Yao <xueyao(a)xyte.ch> Gerrit-CC: clayton craft Gerrit-CC: nullmark <nullmark(a)googlemail.com> Gerrit-CC: slact Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Xue Yao <xueyao(a)xyte.ch> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kilian Neuner <cb(a)9-r.net> Gerrit-Attention: Charles Moyes <thechuckster(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Mon, 25 Apr 2022 08:01:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/craask: Add GPIO table and Fw_config settings
by Tyler Wang (Code Review) 25 Apr '22

25 Apr '22

Tyler Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63817 ) Change subject: mb/google/brya/var/craask: Add GPIO table and Fw_config settings ...................................................................... mb/google/brya/var/craask: Add GPIO table and Fw_config settings 1. Fill GPIO table for Craask. 2. Disable LTE-related GPIOs based on fw_config BUG=None TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Change-Id: I3b85b4b7a68211013f5862d71c8e31ecec41c7b2 --- A src/mainboard/google/brya/variants/craask/Makefile.inc A src/mainboard/google/brya/variants/craask/fw_config.c A src/mainboard/google/brya/variants/craask/gpio.c 3 files changed, 83 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/63817/1 diff --git a/src/mainboard/google/brya/variants/craask/Makefile.inc b/src/mainboard/google/brya/variants/craask/Makefile.inc new file mode 100644 index 0000000..17b1254 --- /dev/null +++ b/src/mainboard/google/brya/variants/craask/Makefile.inc @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/brya/variants/craask/fw_config.c b/src/mainboard/google/brya/variants/craask/fw_config.c new file mode 100644 index 0000000..c475ca3 --- /dev/null +++ b/src/mainboard/google/brya/variants/craask/fw_config.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <bootstate.h> +#include <console/console.h> +#include <fw_config.h> + +static const struct pad_config lte_disable_pads[] = { + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_NC(GPP_A8, NONE), + /* D6 : WWAN_EN */ + PAD_NC(GPP_D6, NONE), + /* F12 : WWAN_RST_L */ + PAD_NC(GPP_F12, NONE), + /* H19 : SOC_I2C_SUB_INT_ODL */ + PAD_NC(GPP_H19, NONE), + /* H23 : WWAN_SAR_DETECT_ODL */ + PAD_NC(GPP_H23, NONE), +}; + +static void fw_config_handle(void *unused) +{ + if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) { + printk(BIOS_INFO, "Disable LTE-related GPIO pins.\n"); + gpio_configure_pads(lte_disable_pads, ARRAY_SIZE(lte_disable_pads)); + } +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/craask/gpio.c b/src/mainboard/google/brya/variants/craask/gpio.c new file mode 100644 index 0000000..93ae776 --- /dev/null +++ b/src/mainboard/google/brya/variants/craask/gpio.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* F12 : GSXDOUT ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_F12, 0, DEEP), + /* H12 : UART0_RTS# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H12, 0, DEEP), + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* D6 : SRCCLKREQ1# ==> WWAN_EN */ + PAD_CFG_GPO(GPP_D6, 1, DEEP), + /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : UART0_CTS# ==> EN_PP3300_SD_X */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* H12 : UART0_RTS# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H12, 1, DEEP), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/63817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b85b4b7a68211013f5862d71c8e31ecec41c7b2 Gerrit-Change-Number: 63817 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/nissa:[TESTONLY] Devicetree WA for debug
by V Sowmya (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: Tim Wawrzynczak. V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63816 ) Change subject: mb/google/nissa:[TESTONLY] Devicetree WA for debug ...................................................................... mb/google/nissa:[TESTONLY] Devicetree WA for debug Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: Id81d9aadbb353746700ddd07da924a59527600c7 --- M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb M src/mainboard/google/brya/variants/nivviks/overridetree.cb 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/63816/1 diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index dfc0a85..2d968a2c 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -117,10 +117,10 @@ device domain 0 on device ref igpu on end device ref dtt on end - device ref tcss_xhci on end + device ref tcss_xhci off end device ref xhci on end device ref shared_sram on end - device ref cnvi_wifi on + device ref cnvi_wifi off chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" device generic 0 on end diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb index 1bb1289..bc4d555 100644 --- a/src/mainboard/google/brya/variants/nivviks/overridetree.cb +++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb @@ -273,9 +273,9 @@ end end end - device ref tcss_xhci on + device ref tcss_xhci off chip drivers/usb/acpi - device ref tcss_root_hub on + device ref tcss_root_hub off chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" -- To view, visit https://review.coreboot.org/c/coreboot/+/63816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id81d9aadbb353746700ddd07da924a59527600c7 Gerrit-Change-Number: 63816 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Sowmya V <v.sowmya(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/nissa:[TESTONLY] WA the FIVR configs
by V Sowmya (Code Review) 25 Apr '22

25 Apr '22

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63815 ) Change subject: mb/google/nissa:[TESTONLY] WA the FIVR configs ...................................................................... mb/google/nissa:[TESTONLY] WA the FIVR configs Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: I3ecbec5408d502c19493937692713a33c0d55ca1 --- M src/mainboard/google/brya/variants/nivviks/overridetree.cb 1 file changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/63815/1 diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb index 03146b5..1bb1289 100644 --- a/src/mainboard/google/brya/variants/nivviks/overridetree.cb +++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb @@ -29,8 +29,12 @@ .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX, - .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, - .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, .v1p05_voltage_mv = 1050, .vnn_voltage_mv = 1050, .vnn_sx_voltage_mv = 1050, -- To view, visit https://review.coreboot.org/c/coreboot/+/63815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ecbec5408d502c19493937692713a33c0d55ca1 Gerrit-Change-Number: 63815 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-CC: Sowmya V <v.sowmya(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Revert CdClock setting
by Angel Pons (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Simon Yang, Kane Chen, Karthik Ramasubramanian. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63808 ) Change subject: soc/intel/jasperlake: Revert CdClock setting ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50d65e0caaf8f3f074322cff5bbdc68bdb1bbf78 Gerrit-Change-Number: 63808 Gerrit-PatchSet: 3 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie.chen(a)intel.com> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-CC: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 25 Apr 2022 07:46:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/block/systemagent: Do more fine grained resource allocation
by Arthur Heymans (Code Review) 25 Apr '22

25 Apr '22

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/59845 ) Change subject: soc/block/systemagent: Do more fine grained resource allocation ...................................................................... Abandoned squashed -- To view, visit https://review.coreboot.org/c/coreboot/+/59845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbceeb31f15ba78c9a241869b5a34cb378096dbb Gerrit-Change-Number: 59845 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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