coreboot-gerrit April 2022

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Change in coreboot[master]: mb/google/dedede/beadrix: Update DPTF setting
by Teddy Shih (Code Review) 25 Apr '22

25 Apr '22

Teddy Shih has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63824 ) Change subject: mb/google/dedede/beadrix: Update DPTF setting ...................................................................... mb/google/dedede/beadrix: Update DPTF setting Update DPTF Policy and temperature sensor values from thermal team. BRANCH=dedede BUG=b:204229229 TEST=on beadrix, verified by FW_NAME=beadrix emerge-dedede coreboot. Signed-off-by: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Change-Id: I34c1298dc8412121f8688842bb8d69d7fafa46f6 --- M src/mainboard/google/dedede/variants/beadrix/overridetree.cb 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/63824/1 diff --git a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb index 8a12e41..f3f5d56 100644 --- a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb +++ b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb @@ -48,14 +48,14 @@ register "options.tsr[0].desc" = ""Memory"" register "options.tsr[1].desc" = ""CPU"" register "policies.passive" = "{ - [0] = DPTF_PASSIVE(CPU, CPU, 80, 4000), - [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 110, 6000), - [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 110, 4000), + [0] = DPTF_PASSIVE(CPU, CPU, 85, 4000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 4000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 4000), }" register "policies.critical" = "{ - [0] = DPTF_CRITICAL(CPU, 110, SHUTDOWN), - [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 110, SHUTDOWN), - [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 110, SHUTDOWN), + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN), }" register "controls.power_limits" = "{ .pl1 = { -- To view, visit https://review.coreboot.org/c/coreboot/+/63824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34c1298dc8412121f8688842bb8d69d7fafa46f6 Gerrit-Change-Number: 63824 Gerrit-PatchSet: 1 Gerrit-Owner: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cmn/cse: Enforce CSE disabling
by Subrata Banik (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: SRIDHAR SIRICILLA, Tim Wawrzynczak, Sridhar Siricilla, Angel Pons, Arthur Heymans, Eric Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63822 ) Change subject: soc/intel/cmn/cse: Enforce CSE disabling ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/63822/comment/8ef7c1c7_d04ea869 PS1, Line 1206: vboot_recovery_mode_enabled() && > Ack @Sridhar, can you please create a bug so that we can capture this change request and you can update the document with an ETA. Also, looking for your response to avoid 2 questions. if we can remove CSE Lite check from cse_eop.c as well ? -- To view, visit https://review.coreboot.org/c/coreboot/+/63822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77c254195895a93a5606adee8b6f43d8b7100848 Gerrit-Change-Number: 63822 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 25 Apr 2022 11:41:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/cse: Enforce CSE disabling
by Sridhar Siricilla (Code Review) 25 Apr '22

25 Apr '22

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Change in coreboot[master]: soc/intel/cmn/cse: Drop redundant macro check for heci1_disable()
by Sridhar Siricilla (Code Review) 25 Apr '22

25 Apr '22

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Change in coreboot[master]: soc/intel: Decouple HECI disabling interface from HECI disable Kconfig
by Sridhar Siricilla (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: SRIDHAR SIRICILLA, Subrata Banik, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai, Andrey Petrov. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63823 ) Change subject: soc/intel: Decouple HECI disabling interface from HECI disable Kconfig ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63823 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66abc04d5e195515165a77b0166d004f17d029e7 Gerrit-Change-Number: 63823 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Mon, 25 Apr 2022 11:36:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/cse: Drop redundant macro check for heci1_disable()
by Subrata Banik (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: SRIDHAR SIRICILLA, Tim Wawrzynczak, Sridhar Siricilla, Angel Pons, Arthur Heymans, Eric Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63821 ) Change subject: soc/intel/cmn/cse: Drop redundant macro check for heci1_disable() ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/common/block/cse/disable_heci.c: https://review.coreboot.org/c/coreboot/+/63821/comment/e0f10957_679a109f PS6, Line 86: if (ENV_SMM && CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_SBI)) { : printk(BIOS_INFO, "Disabling Heci using SBI in SMM mode\n"); : return heci1_disable_using_sbi(); : } else if (!ENV_SMM && CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC)) { : printk(BIOS_INFO, "Disabling Heci using PMC IPC\n"); : return heci1_disable_using_pmc(); : } else if (!ENV_SMM && CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR)) { : printk(BIOS_INFO, "Disabling Heci using PCR\n"); : return heci1_disable_using_pcr(); > All KConfigs have been linked with DISABLE_HECI1_AT_PRE_BOOT flag, so the change is still doesn't disable the HECI1 interface :( Pick this patch train completely CB:63823 is added to address this feedback. -- To view, visit https://review.coreboot.org/c/coreboot/+/63821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47d7a9989e355987618d089f79c3340fcf4953ad Gerrit-Change-Number: 63821 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 25 Apr 2022 11:33:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Decouple HECI disabling interface from HECI disable Kconfig
by Subrata Banik (Code Review) 25 Apr '22

25 Apr '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63823 ) Change subject: soc/intel: Decouple HECI disabling interface from HECI disable Kconfig ...................................................................... soc/intel: Decouple HECI disabling interface from HECI disable Kconfig This patch decouples HECI disabling interface a.k.a PCR or PMC IPC etc. from DISABLE_HECI1_AT_PRE_BOOT kconfig as Intel ME BWG recommends to disable the CSE PCI device while CSE is in SOFT TEMP DISABLE state. TEST=Able to build google/redrix. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I66abc04d5e195515165a77b0166d004f17d029e7 --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig 5 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/63823/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index dbcb509..b90ec1a 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -88,7 +88,7 @@ select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_SCS if SOC_INTEL_ALDERLAKE_PCH_N select SOC_INTEL_COMMON_BLOCK_HDA - select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT + select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_COMMON_BLOCK_IRQ select SOC_INTEL_COMMON_BLOCK_MEMINIT diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index b2235f8..a6ff1d5 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -82,7 +82,7 @@ select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY select SOC_INTEL_COMMON_BLOCK_GRAPHICS - select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR if DISABLE_HECI1_AT_PRE_BOOT + select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR select SOC_INTEL_COMMON_BLOCK_ITSS select SOC_INTEL_COMMON_BLOCK_I2C select SOC_INTEL_COMMON_BLOCK_LPC diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index ddb1619..eafd63f 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -25,7 +25,7 @@ select HAVE_INTEL_FSP_REPO select PMC_IPC_ACPI_INTERFACE if DISABLE_HECI1_AT_PRE_BOOT select SOC_INTEL_CONFIGURE_DDI_A_4_LANES - select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT + select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU config SOC_INTEL_COMETLAKE_1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 692a15b..520a5a0 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -63,7 +63,7 @@ select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL select SOC_INTEL_COMMON_BLOCK_GSPI select SOC_INTEL_COMMON_BLOCK_HDA - select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR if DISABLE_HECI1_AT_PRE_BOOT + select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SCS diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index ac175c4..674e744 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -61,7 +61,7 @@ select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA - select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT + select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC select SOC_INTEL_COMMON_BLOCK_IRQ select SOC_INTEL_COMMON_BLOCK_MEMINIT select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63823 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66abc04d5e195515165a77b0166d004f17d029e7 Gerrit-Change-Number: 63823 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cmn/cse: Drop redundant macro check for heci1_disable()
by Sridhar Siricilla (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: SRIDHAR SIRICILLA, Subrata Banik, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63821 ) Change subject: soc/intel/cmn/cse: Drop redundant macro check for heci1_disable() ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/cse/disable_heci.c: https://review.coreboot.org/c/coreboot/+/63821/comment/89219901_a680f73a PS6, Line 86: if (ENV_SMM && CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_SBI)) { : printk(BIOS_INFO, "Disabling Heci using SBI in SMM mode\n"); : return heci1_disable_using_sbi(); : } else if (!ENV_SMM && CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC)) { : printk(BIOS_INFO, "Disabling Heci using PMC IPC\n"); : return heci1_disable_using_pmc(); : } else if (!ENV_SMM && CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR)) { : printk(BIOS_INFO, "Disabling Heci using PCR\n"); : return heci1_disable_using_pcr(); All KConfigs have been linked with DISABLE_HECI1_AT_PRE_BOOT flag, so the change is still doesn't disable the HECI1 interface :( -- To view, visit https://review.coreboot.org/c/coreboot/+/63821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47d7a9989e355987618d089f79c3340fcf4953ad Gerrit-Change-Number: 63821 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 25 Apr 2022 11:08:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/cse: Enforce CSE disabling
by Subrata Banik (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: SRIDHAR SIRICILLA, Tim Wawrzynczak, Sridhar Siricilla, Angel Pons, Arthur Heymans, Eric Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63822 ) Change subject: soc/intel/cmn/cse: Enforce CSE disabling ...................................................................... Patch Set 2: (2 comments) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/63822/comment/b2be2e7d_e03b9477 PS1, Line 1200: SOC_INTEL_CSE_LITE_SKU > > No need to limit the logic to CSE Lite . This is still applicable for Consumer SKU as well. […] Ack https://review.coreboot.org/c/coreboot/+/63822/comment/6db0ee14_aeb14ecc PS1, Line 1206: vboot_recovery_mode_enabled() && > > vboot_recovery_mode_enabled() is not required. Please see above comment. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/63822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77c254195895a93a5606adee8b6f43d8b7100848 Gerrit-Change-Number: 63822 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 25 Apr 2022 10:41:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/cse: Enforce CSE disabling
by Subrata Banik (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: SRIDHAR SIRICILLA, Tim Wawrzynczak, Sridhar Siricilla, Angel Pons, Arthur Heymans, Eric Lai. Hello build bot (Jenkins), SRIDHAR SIRICILLA, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63822 to look at the new patch set (#2). Change subject: soc/intel/cmn/cse: Enforce CSE disabling ...................................................................... soc/intel/cmn/cse: Enforce CSE disabling This patch enforces disabling of the CSE device if CSE stays in SOFT TEMP DISABLE state. The recommendation is to make CSE function disable to avoid receiving any CSE commands from the OS layer. TEST=None Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I77c254195895a93a5606adee8b6f43d8b7100848 --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/63822/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77c254195895a93a5606adee8b6f43d8b7100848 Gerrit-Change-Number: 63822 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit April 2022