coreboot-gerrit April 2022

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Change in coreboot[master]: soc/intel/alderlake/acpi/gpio.asl: Add missing GPIO communities
by Michał Żygowski (Code Review) 25 Apr '22

25 Apr '22

Michał Żygowski has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/63787 ) Change subject: soc/intel/alderlake/acpi/gpio.asl: Add missing GPIO communities ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/63787 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bb5a5d7732c16074c5d517ac21e24de9a898403 Gerrit-Change-Number: 63787 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: xcompile: Hard-code gcc-12
by Paul Menzel (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: Martin L Roth. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62831 ) Change subject: xcompile: Hard-code gcc-12 ...................................................................... Patch Set 1: (2 comments) Patchset: PS1: Thank you for your suggestions. File util/xcompile/xcompile: https://review.coreboot.org/c/coreboot/+/62831/comment/79cdde09_a1898c70 PS1, Line 64: gcc-12 > I'm not sure that this is what we want here. What about other systems than debian? […] I have to read up, what `HOSTCC` is used for again. (Only to build stuff in `utils/` or also to build coreboot itself?) What I ideally would like to have is to directly set the compiler executable (and other utils) normally done by setting `CC` in Autotools and “standard” Makefiles: make CC=gcc-12 -- To view, visit https://review.coreboot.org/c/coreboot/+/62831 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8c38cbe2f76350eda7f36861523a5012a13fc0b Gerrit-Change-Number: 62831 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Comment-Date: Mon, 25 Apr 2022 08:54:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/pc80/vga: Use write to fix array out of bounds warning
by Paul Menzel (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: Martin L Roth. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62829 ) Change subject: drivers/pc80/vga: Use write to fix array out of bounds warning ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62829/comment/489900a9_2d75744c PS1, Line 10: x86_64-linux-gnu-gcc-12 -MMD -Isrc -Isrc/include -Isrc/commonlib/include -Isrc/commonlib/bsd/include -Ibuild -I3rdparty/vboot/firmware/include -include src/include/kconfig.h -include src/include/rules.h -include src/commonlib/bsd/include/commonlib/bsd/compiler.h -I3rdparty -D__BUILD_DIR__=\"build\" -Isrc/arch/x86/include -D__ARCH_x86_32__ -pipe -g -nostdinc -std=gnu11 -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough -Wshadow -Wdate-time -Wtype-limits -Wvla -Wdangling-else -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie -Wno-packed-not-aligned -fconserve-stack -Wnull-dereference -Wreturn-type -Wlogical-op -Wduplicated-cond -Wno-unused-but-set-variable -Werror -Os -Wno-address-of-packed-member -m32 -Wl,-b,elf32-i386 -Wl,-melf_i386 -m32 -fuse-ld=bfd -fno-stack-protector -Wl,--build-id=none -fno-delete-null-pointer-checks -Wlogical-op -march=i686 -mno-mmx -MT build/ramstage/drivers/pc80/vga/vga.o -D__RAMSTAGE__ -c -o build/ramstage/drivers/pc80/vga/vga.o src/drivers/pc80/vga/vga.c > Maybe remove this? It doesn't really contribute anything. Yes, will do. Its intended use was to show that x86_64-linux-gnu-gcc-12 was indeed used as the compiler. -- To view, visit https://review.coreboot.org/c/coreboot/+/62829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb60fb4ca08ae39a8628bc2543417819ee9dcbb2 Gerrit-Change-Number: 62829 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Comment-Date: Mon, 25 Apr 2022 08:50:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Updated Protectli fw6b documentations
by Paul Menzel (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: Xue Yao. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63016 ) Change subject: Documentation: Updated Protectli fw6b documentations ...................................................................... Patch Set 3: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63016/comment/d67ba09c_607d49a1 PS3, Line 7: Updated As felix suggested, please use imperative mood: Update. [1] [1]: https://cbea.ms/git-commit/ https://review.coreboot.org/c/coreboot/+/63016/comment/d4ef6545_ef3cbba8 PS3, Line 9: Updated Ditto. https://review.coreboot.org/c/coreboot/+/63016/comment/76c655ff_76e6a7c0 PS3, Line 11: has also been is Patchset: PS3: Thank you for the update. You can mark the comments you acted upon as resolved yourself. File Documentation/mainboard/protectli/fw6.md: https://review.coreboot.org/c/coreboot/+/63016/comment/013613cd_ae8ced33 PS3, Line 51: website Web site -- To view, visit https://review.coreboot.org/c/coreboot/+/63016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4938d81d57fc8172fefcc00222806fff0735d503 Gerrit-Change-Number: 63016 Gerrit-PatchSet: 3 Gerrit-Owner: Xue Yao <xueyao(a)xyte.ch> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Xue Yao <xueyao(a)xyte.ch> Gerrit-Comment-Date: Mon, 25 Apr 2022 08:48:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Fix buggy code tries to access DESC region
by Sridhar Siricilla (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: Arthur Heymans. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63734 ) Change subject: soc/intel/common: Fix buggy code tries to access DESC region ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/basecode/debug/debug_feature.c: https://review.coreboot.org/c/coreboot/+/63734/comment/82f3c492_08ea4936 PS6, Line 26: boot_device_ro > You are right, boot_device_rw() also works. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/63734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib144cc0845b7527e5a3032529b0802f961944b87 Gerrit-Change-Number: 63734 Gerrit-PatchSet: 6 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 25 Apr 2022 08:39:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Fix buggy code tries to access DESC region
by Sridhar Siricilla (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: Arthur Heymans. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63734 ) Change subject: soc/intel/common: Fix buggy code tries to access DESC region ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/basecode/debug/debug_feature.c: https://review.coreboot.org/c/coreboot/+/63734/comment/acd7bcd1_42f4451e PS6, Line 26: boot_device_ro > actually does boot_device_rw() not work? Then you only need to change one line. You are right, boot_device_rw() also works. -- To view, visit https://review.coreboot.org/c/coreboot/+/63734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib144cc0845b7527e5a3032529b0802f961944b87 Gerrit-Change-Number: 63734 Gerrit-PatchSet: 6 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 25 Apr 2022 08:38:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/nissa/var/craask: Add device settings
by Tyler Wang (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63818 to look at the new patch set (#2). Change subject: mb/google/nissa/var/craask: Add device settings ...................................................................... mb/google/nissa/var/craask: Add device settings Add the configuration in device tree: 1. Add speaker codec and speaker amp settings 2. Add Elan touchscreen settings 3. Add WFC and USB settings 4 Add Elan Touchpad settings 5. Add WLAN configuration 6. Add LTE configuration BUG=b:229938024 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Change-Id: I7bb2e102640379a498920d76d42c15843e4bfc8d --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/craask/overridetree.cb 2 files changed, 360 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/63818/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63818 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bb2e102640379a498920d76d42c15843e4bfc8d Gerrit-Change-Number: 63818 Gerrit-PatchSet: 2 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/nissa/var/craask: Add device settings
by Tyler Wang (Code Review) 25 Apr '22

25 Apr '22

Tyler Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63818 ) Change subject: mb/google/nissa/var/craask: Add device settings ...................................................................... mb/google/nissa/var/craask: Add device settings Add the configuration in device tree: 1. Add speaker codec and speaker amp settings 2. Add Elan touchscreen settings 3. Add WFC and USB settings 4 Add Elan Touchpad settings 5. Add WLAN configuration 6. Add LTE configuration BUG=b:229938024 TEST=emerge-nissa coreboot Change-Id: I7bb2e102640379a498920d76d42c15843e4bfc8d --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/craask/overridetree.cb 2 files changed, 360 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/63818/1 diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index ae5314c..dfa8986 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -199,6 +199,10 @@ config BOARD_GOOGLE_CRAASK bool "-> Craask" select BOARD_GOOGLE_BASEBOARD_NISSA + select DRIVERS_GENERIC_GPIO_KEYS + select DRIVERS_GENESYSLOGIC_GL9750 + select DRIVERS_INTEL_MIPI_CAMERA + select HAVE_WWAN_POWER_SEQUENCE config BOARD_GOOGLE_OSIRIS bool "-> Osiris" diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb index 4f2c04a..6a36fda 100644 --- a/src/mainboard/google/brya/variants/craask/overridetree.cb +++ b/src/mainboard/google/brya/variants/craask/overridetree.cb @@ -1,6 +1,360 @@ +fw_config + field DB_USB 0 1 + option DB_NONE 0 + option DB_1C_1A 1 + option DB_1C_LTE 2 + end +end + chip soc/intel/alderlake + register "sagv" = "SaGv_Enabled" - device domain 0 on - end + # SOC Aux orientation override: + # This is a bitfield that corresponds to up to 4 TCSS ports. + # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. + # TcssAuxOri = 0101b + # Bit0,Bit2 set to "1" indicates no retimer on USBC Ports + # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the + # motherboard to USBC connector + register "tcss_aux_ori" = "5" + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" + + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + + device domain 0 on + device ref ipu on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "1" + register "cio2_lanes_used" = "{2}" # 2 CSI Camera lanes are used + register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0"" + register "cio2_prt[0]" = "1" + device generic 0 on end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN6915"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_delay_ms" = "280" + register "generic.stop_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F13)" + register "key.wake_gpe" = "GPE0_DW2_15" + register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end + device ref i2c2 on + chip drivers/i2c/sx9324 + register "desc" = ""SAR Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "1" + register "reg_gnrl_ctrl0" = "0x16" + register "reg_gnrl_ctrl1" = "0x21" + register "reg_afe_ctrl0" = "0x00" + register "reg_afe_ctrl1" = "0x10" + register "reg_afe_ctrl2" = "0x00" + register "reg_afe_ctrl3" = "0x00" + register "reg_afe_ctrl4" = "0x07" + register "reg_afe_ctrl5" = "0x00" + register "reg_afe_ctrl6" = "0x00" + register "reg_afe_ctrl7" = "0x07" + register "reg_afe_ctrl8" = "0x12" + register "reg_afe_ctrl9" = "0x0f" + register "reg_prox_ctrl0" = "0x12" + register "reg_prox_ctrl1" = "0x12" + register "reg_prox_ctrl2" = "0x90" + register "reg_prox_ctrl3" = "0x60" + register "reg_prox_ctrl4" = "0x0c" + register "reg_prox_ctrl5" = "0x12" + register "reg_prox_ctrl6" = "0x3c" + register "reg_prox_ctrl7" = "0x58" + register "reg_adv_ctrl0" = "0x00" + register "reg_adv_ctrl1" = "0x00" + register "reg_adv_ctrl2" = "0x00" + register "reg_adv_ctrl3" = "0x00" + register "reg_adv_ctrl4" = "0x00" + register "reg_adv_ctrl5" = "0x05" + register "reg_adv_ctrl6" = "0x00" + register "reg_adv_ctrl7" = "0x00" + register "reg_adv_ctrl8" = "0x00" + register "reg_adv_ctrl9" = "0x00" + register "reg_adv_ctrl10" = "0x5c" + register "reg_adv_ctrl11" = "0x52" + register "reg_adv_ctrl12" = "0xb5" + register "reg_adv_ctrl13" = "0x00" + register "reg_adv_ctrl14" = "0x80" + register "reg_adv_ctrl15" = "0x0c" + register "reg_adv_ctrl16" = "0x38" + register "reg_adv_ctrl17" = "0x56" + register "reg_adv_ctrl18" = "0x33" + register "reg_adv_ctrl19" = "0xf0" + register "reg_adv_ctrl20" = "0xf0" + device i2c 28 on + probe DB_USB DB_1C_LTE + end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI5675"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 5675 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "ssdb.link_used" = "1" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "1" + register "link_freq[0]" = "DEFAULT_LINK_FREQ" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" + register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_WCAM_X + register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" # EN_PP1800_PP1200_WCAM_X + register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" # WCAM_RST_L + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "3" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW AF DAC"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC"" + register "vcm_compat" = ""dongwoon,dw9714"" + + device i2c 0C on end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" + register "acpi_uid" = "1" + register "acpi_name" = ""NVM0"" + register "chip_name" = ""GT24C08"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref xhci on + device i2c 50 on end + end + end + device ref i2c3 on + chip drivers/i2c/nau8825 + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)" + register "jkdet_enable" = "1" + register "jkdet_pull_enable" = "0" + register "jkdet_polarity" = "1" # ActiveLow + register "vref_impedance" = "2" # 125kOhm + register "micbias_voltage" = "6" # 2.754 + register "sar_threshold_num" = "4" + register "sar_threshold[0]" = "0x0c" + register "sar_threshold[1]" = "0x1c" + register "sar_threshold[2]" = "0x38" + register "sar_threshold[3]" = "0x60" + register "sar_hysteresis" = "1" + register "sar_voltage" = "0" # VDDA + register "sar_compare_time" = "0" # 500ns + register "sar_sampling_time" = "0" # 2us + register "short_key_debounce" = "2" # 100ms + register "jack_insert_debounce" = "7" # 512ms + register "jack_eject_debounce" = "7" # 512ms + device i2c 1a on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "probed" = "1" + device i2c 15 on end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port4 on + probe DB_USB DB_1C_1A + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port4 on + probe DB_USB DB_1C_LTE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb3_port2 on + probe DB_USB DB_1C_1A + end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port2 on + probe DB_USB DB_1C_LTE + end + end + end + end + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/63818 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bb2e102640379a498920d76d42c15843e4bfc8d Gerrit-Change-Number: 63818 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/systemagent.c: Optimize resources for MTRR solution
by Arthur Heymans (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: Werner Zeh, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59917 ) Change subject: soc/intel/systemagent.c: Optimize resources for MTRR solution ...................................................................... Patch Set 4: Code-Review-1 (1 comment) Patchset: PS4: This is not quite right. -- To view, visit https://review.coreboot.org/c/coreboot/+/59917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11c910d1002bcf6e782d89a209d12d12bebb45d4 Gerrit-Change-Number: 59917 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 25 Apr 2022 08:21:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/pineview: Use cbfs mcache
by Angel Pons (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: Damien Zammit, Arthur Heymans, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52941 ) Change subject: nb/intel/pineview: Use cbfs mcache ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1487ba9decd3aa22424a3ac111de7fbdb867d38d Gerrit-Change-Number: 52941 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 25 Apr 2022 08:19:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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