coreboot-gerrit April 2022

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Change in coreboot[master]: soc/intel/cmn/cse: Drop redundant macro check for heci1_disable()
by Subrata Banik (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: SRIDHAR SIRICILLA, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai. Hello build bot (Jenkins), SRIDHAR SIRICILLA, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63821 to look at the new patch set (#6). Change subject: soc/intel/cmn/cse: Drop redundant macro check for heci1_disable() ...................................................................... soc/intel/cmn/cse: Drop redundant macro check for heci1_disable() This patch removes redundant DISABLE_HECI1_AT_PRE_BOOT config check for heci1_disable(), once by caller (from various SoC) and again inside the callee (heci1_disable) function. As all callers of heci1_disable() function are doing DISABLE_HECI1_AT_PRE_BOOT config enabled check, hence, the second check inside the callee can be dropped. TEST=Able to build and boot google/redrix with this change. CSE PCI device is getting function disabled upon selecting DISABLE_HECI1_AT_PRE_BOOT from SoC config. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I47d7a9989e355987618d089f79c3340fcf4953ad --- M src/soc/intel/common/block/cse/disable_heci.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/63821/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/63821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47d7a9989e355987618d089f79c3340fcf4953ad Gerrit-Change-Number: 63821 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cmn/cse: Enforce CSE disabling
by Subrata Banik (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: SRIDHAR SIRICILLA, Tim Wawrzynczak, Sridhar Siricilla, Angel Pons, Arthur Heymans, Eric Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63822 ) Change subject: soc/intel/cmn/cse: Enforce CSE disabling ...................................................................... Patch Set 1: (2 comments) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/63822/comment/8ef17ba9_ebef1bb4 PS1, Line 1200: SOC_INTEL_CSE_LITE_SKU > No need to limit the logic to CSE Lite . This is still applicable for Consumer SKU as well. If CSE's current operation mode is Soft Temp Disable, BIOS still needs to disable the HECI1 interface. sure, can we drop the same from below code as well? https://github.com/coreboot/coreboot/blob/master/src/soc/intel/common/block… as well? https://review.coreboot.org/c/coreboot/+/63822/comment/0b10095d_92202db1 PS1, Line 1206: vboot_recovery_mode_enabled() && > vboot_recovery_mode_enabled() is not required. Please see above comment. can we remove this vboot function check from https://github.com/coreboot/coreboot/blob/master/src/soc/intel/common/block… as well. in that case only one `if` clause can serve our purpose https://github.com/coreboot/coreboot/blob/master/src/soc/intel/common/block… isn't it ? -- To view, visit https://review.coreboot.org/c/coreboot/+/63822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77c254195895a93a5606adee8b6f43d8b7100848 Gerrit-Change-Number: 63822 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 25 Apr 2022 10:34:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/cse: Enforce CSE disabling
by Sridhar Siricilla (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: SRIDHAR SIRICILLA, Subrata Banik, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63822 ) Change subject: soc/intel/cmn/cse: Enforce CSE disabling ...................................................................... Patch Set 1: (2 comments) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/63822/comment/9aeff664_06923bc8 PS1, Line 1200: SOC_INTEL_CSE_LITE_SKU No need to limit the logic to CSE Lite . This is still applicable for Consumer SKU as well. If CSE's current operation mode is Soft Temp Disable, BIOS still needs to disable the HECI1 interface. https://review.coreboot.org/c/coreboot/+/63822/comment/42615a30_5ac8fc4e PS1, Line 1206: vboot_recovery_mode_enabled() && vboot_recovery_mode_enabled() is not required. Please see above comment. -- To view, visit https://review.coreboot.org/c/coreboot/+/63822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77c254195895a93a5606adee8b6f43d8b7100848 Gerrit-Change-Number: 63822 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 25 Apr 2022 10:29:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/cse: Drop redundant macro check for heci1_disable()
by Subrata Banik (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: SRIDHAR SIRICILLA, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai. Hello SRIDHAR SIRICILLA, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63821 to look at the new patch set (#5). Change subject: soc/intel/cmn/cse: Drop redundant macro check for heci1_disable() ...................................................................... soc/intel/cmn/cse: Drop redundant macro check for heci1_disable() This patch removes redundant DISABLE_HECI1_AT_PRE_BOOT config check for heci1_disable(), once by caller (from various SoC) and again inside the callee (heci1_disable) function. As all callers of heci1_disable() function are doing DISABLE_HECI1_AT_PRE_BOOT config enabled check, hence, the second check inside the callee can be dropped. TEST=Able to build and boot google/redrix with this change. CSE PCI device is getting function disabled upon selecting DISABLE_HECI1_AT_PRE_BOOT from SoC config. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I47d7a9989e355987618d089f79c3340fcf4953ad --- M src/soc/intel/common/block/cse/disable_heci.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/63821/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/63821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47d7a9989e355987618d089f79c3340fcf4953ad Gerrit-Change-Number: 63821 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cmn/cse: Drop redundant macro check for heci1_disable()
by Subrata Banik (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: SRIDHAR SIRICILLA, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai. Hello SRIDHAR SIRICILLA, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63821 to look at the new patch set (#4). Change subject: soc/intel/cmn/cse: Drop redundant macro check for heci1_disable() ...................................................................... soc/intel/cmn/cse: Drop redundant macro check for heci1_disable() This patch removes redundant DISABLE_HECI1_AT_PRE_BOOT config check for heci1_disable(), once by caller (from various SoC) and again inside the called (heci1_disable) function. As all callers of heci1_disable() function are doing DISABLE_HECI1_AT_PRE_BOOT config enabled check, hence, the second check inside the heci1_disable() can be dropped. TEST=Able to build and boot google/redrix with this change. CSE PCI device is getting function disabled upon selecting DISABLE_HECI1_AT_PRE_BOOT from SoC config. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I47d7a9989e355987618d089f79c3340fcf4953ad --- M src/soc/intel/common/block/cse/disable_heci.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/63821/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/63821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47d7a9989e355987618d089f79c3340fcf4953ad Gerrit-Change-Number: 63821 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cmn/cse: Drop redundant macro check for heci1_disable()
by Subrata Banik (Code Review) 25 Apr '22

25 Apr '22

Attention is currently required from: SRIDHAR SIRICILLA, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai. Hello SRIDHAR SIRICILLA, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63821 to look at the new patch set (#3). Change subject: soc/intel/cmn/cse: Drop redundant macro check for heci1_disable() ...................................................................... soc/intel/cmn/cse: Drop redundant macro check for heci1_disable() This patch removes redundant DISABLE_HECI1_AT_PRE_BOOT config check for heci1_disable(), once by caller and once inside the called function. As all callers of heci1_disable() function are doing DISABLE_HECI1_AT_PRE_BOOT config enabled check, hence, the second check inside the callee can be dropped. TEST=Able to build and boot google/redrix with this change. CSE PCI device is getting function disabled upon selecting DISABLE_HECI1_AT_PRE_BOOT from SoC config. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I47d7a9989e355987618d089f79c3340fcf4953ad --- M src/soc/intel/common/block/cse/disable_heci.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/63821/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47d7a9989e355987618d089f79c3340fcf4953ad Gerrit-Change-Number: 63821 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cmn/cse: Drop redundant macro check for heci1_disable()
by Subrata Banik (Code Review) 25 Apr '22

25 Apr '22

Subrata Banik has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/63821 ) Change subject: soc/intel/cmn/cse: Drop redundant macro check for heci1_disable() ...................................................................... soc/intel/cmn/cse: Drop redundant macro check for heci1_disable() This patch removes redundant DISABLE_HECI1_AT_PRE_BOOT config check for heci1_disable(), once by caller and once inside the callee function. As all callers of heci1_disable() function are doing DISABLE_HECI1_AT_PRE_BOOT config enabled check, hence, the second check inside the callee can be dropped. TEST=Able to build and boot google/redrix with this change. CSE PCI device is getting function disabled upon selecting DISABLE_HECI1_AT_PRE_BOOT from SoC config. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I47d7a9989e355987618d089f79c3340fcf4953ad --- M src/soc/intel/common/block/cse/disable_heci.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/63821/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47d7a9989e355987618d089f79c3340fcf4953ad Gerrit-Change-Number: 63821 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cmn/cse: Enforce CSE disabling
by Subrata Banik (Code Review) 25 Apr '22

25 Apr '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63822 ) Change subject: soc/intel/cmn/cse: Enforce CSE disabling ...................................................................... soc/intel/cmn/cse: Enforce CSE disabling This patch enforces disabling of the CSE device if a platform meets below scenarios: 1. Platform is booting with CSE-Lite SKU. 2. Platform is running CSE RO FW and the board is booted into the ChromeOS recovery mode. In that case the CSE is expected to be in SOFT TEMP DISABLE state, hence, recommended to make CSE function disable to avoid receiving any CSE commands from the OS layer. TEST=None Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I77c254195895a93a5606adee8b6f43d8b7100848 --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/63822/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 64fd041..e1b4319 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1195,6 +1195,23 @@ me_reset_with_count(); } +static bool cse_set_to_disable(void) +{ + if (!CONFIG(SOC_INTEL_CSE_LITE_SKU)) + return false; + + /* For a CSE-Lite SKU, if the CSE is running RO FW and the board is + running vboot in recovery mode, the CSE is expected to be in SOFT + TEMP DISABLE state. */ + if (vboot_recovery_mode_enabled() && cse_is_hfs1_com_soft_temp_disable()) { + printk(BIOS_INFO, "HECI: coreboot in recovery mode; found CSE in expected SOFT " + "TEMP DISABLE state, disabling CSE\n"); + return true; + } + + return false; +} + /* * `cse_final_ready_to_boot` function is native implementation of equivalent events * performed by FSP NotifyPhase(Ready To Boot) API invocations. @@ -1212,7 +1229,7 @@ cse_control_global_reset_lock(); - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) { + if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) || cse_set_to_disable()) { cse_set_to_d0i3(); heci1_disable(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/63822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77c254195895a93a5606adee8b6f43d8b7100848 Gerrit-Change-Number: 63822 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cmn/cse: Remove `DISABLE_HECI1_AT_PRE_BOOT` check inside he...
by Subrata Banik (Code Review) 25 Apr '22

25 Apr '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63821 ) Change subject: soc/intel/cmn/cse: Remove `DISABLE_HECI1_AT_PRE_BOOT` check inside heci1_disable() ...................................................................... soc/intel/cmn/cse: Remove `DISABLE_HECI1_AT_PRE_BOOT` check inside heci1_disable() This patch removes redundant DISABLE_HECI1_AT_PRE_BOOT config check for heci1_disable(), once by caller and once inside the callee function. As all callers of heci1_disable() function are doing DISABLE_HECI1_AT_PRE_BOOT config enabled check, hence, the second check inside the callee can be dropped. TEST=Able to build and boot google/redrix with this change. CSE PCI device is getting function disabled upon selecting DISABLE_HECI1_AT_PRE_BOOT from SoC config. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I47d7a9989e355987618d089f79c3340fcf4953ad --- M src/soc/intel/common/block/cse/disable_heci.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/63821/1 diff --git a/src/soc/intel/common/block/cse/disable_heci.c b/src/soc/intel/common/block/cse/disable_heci.c index 84a09fd..625de75 100644 --- a/src/soc/intel/common/block/cse/disable_heci.c +++ b/src/soc/intel/common/block/cse/disable_heci.c @@ -83,9 +83,6 @@ void heci1_disable(void) { - if (!CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) - return; - if (ENV_SMM && CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_SBI)) { printk(BIOS_INFO, "Disabling Heci using SBI in SMM mode\n"); return heci1_disable_using_sbi(); -- To view, visit https://review.coreboot.org/c/coreboot/+/63821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47d7a9989e355987618d089f79c3340fcf4953ad Gerrit-Change-Number: 63821 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake/acpi/gpio.asl: Add missing GPIO communities
by Michał Żygowski (Code Review) 25 Apr '22

25 Apr '22

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63787 ) Change subject: soc/intel/alderlake/acpi/gpio.asl: Add missing GPIO communities ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > I believe it is intentional that community 2 and 3 are left out of the ASL, they are not usually exp […] You are right, there is no need. I noticed an error in dmesg saying invalid CRS resource for alderlake pinctrl and thought it was the missing communities. It may be due to an older kernel or something. Kernel 5.17 doesn't show the error without this patch. Abandoning it -- To view, visit https://review.coreboot.org/c/coreboot/+/63787 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bb5a5d7732c16074c5d517ac21e24de9a898403 Gerrit-Change-Number: 63787 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Apr 2022 10:05:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit April 2022