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Change in coreboot[master]: arch,cpu,lib: Use thin archives instead of partial linking
by Jacob Garber (Code Review) 09 May '22

09 May '22

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40812 ) Change subject: arch,cpu,lib: Use thin archives instead of partial linking ...................................................................... arch,cpu,lib: Use thin archives instead of partial linking x86 ramstage and smm compilation currently use partial linking, which is not supported by link-time optimization. Collect the object files into thin archives instead, and link them all at once at the very end. Change-Id: I122a4542d1e98d89545897d5177c93ee463d0cdb Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M src/arch/x86/Makefile.inc M src/cpu/x86/smm/Makefile.inc M src/lib/Makefile.inc 3 files changed, 17 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/40812/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index af52f70..1615e75 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -307,18 +307,20 @@ endif -$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(call src-to-obj,ramstage,src/arch/x86/memlayout.ld) - @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(call src-to-obj,ramstage,src/arch/x86/memlayout.ld) - -$(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs) - @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) - $(LD_ramstage) -Wl,-m,elf_i386 -r -o $@ $(COMPILER_RT_FLAGS_ramstage) -Wl,--whole-archive,--start-group $(filter-out %.ld,$(ramstage-objs)) $(ramstage-libs) -Wl,--no-whole-archive $(COMPILER_RT_ramstage) -Wl,--end-group +LDFLAGS_ramstage += -Wl,-m,elf_i386 else - $(LD_ramstage) -Wl,-m,elf_x86_64 -r -o $@ $(COMPILER_RT_FLAGS_ramstage) -Wl,--whole-archive,--start-group $(filter-out %.ld,$(ramstage-objs)) $(ramstage-libs) -Wl,--no-whole-archive $(COMPILER_RT_ramstage) -Wl,--end-group +LDFLAGS_ramstage += -Wl,-m,elf_x86_64 endif +$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.a $(call src-to-obj,ramstage,src/arch/x86/memlayout.ld) + @printf " CC $(subst $(obj)/,,$(@))\n" + $(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) $(COMPILER_RT_FLAGS_ramstage) -o $@ -L$(obj) -Wl,--whole-archive,--start-group $< -Wl,--no-whole-archive $(COMPILER_RT_ramstage) -Wl,--end-group -T $(call src-to-obj,ramstage,src/arch/x86/memlayout.ld) + +$(objgenerated)/ramstage.a: $$(ramstage-objs) $$(ramstage-libs) + @printf " AR $(subst $(obj)/,,$(@))\n" + $(AR_ramstage) rcT $@ $(filter-out %.ld,$(ramstage-objs)) $(ramstage-libs) + endif # CONFIG_ARCH_RAMSTAGE_X86_32 / CONFIG_ARCH_RAMSTAGE_X86_64 smm-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 2e63fb3..4899370 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -25,8 +25,8 @@ smm-generic-ccopts += -D__SMM__ smm-c-deps:=$$(OPTION_TABLE_H) -$(obj)/smm/smm.o: $$(smm-objs) $(COMPILER_RT_smm) - $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) -Wl,--whole-archive,--start-group $(smm-objs) -Wl,--no-whole-archive $(COMPILER_RT_smm) -Wl,--end-group +$(obj)/smm/smm.a: $$(smm-objs) + $(AR_smm) rcT $@ $^ # change to the target path because objcopy will use the path name in its # ELF symbol names. @@ -72,9 +72,9 @@ # C-based SMM handler. ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) -$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_32)) +$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.a, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_32)) else -$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_64)) +$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.a, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_64)) endif $(obj)/smm/smm: $(obj)/smm/smm.elf.rmod @@ -82,8 +82,8 @@ else # CONFIG_SMM_TSEG -$(obj)/smm/smm: $(obj)/smm/smm.o $(src)/cpu/x86/smm/smm.ld - $(LD_smm) $(LDFLAGS_smm) -o $(obj)/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/smm/smm.o +$(obj)/smm/smm: $(obj)/smm/smm.a $(src)/cpu/x86/smm/smm.ld + $(LD_smm) $(LDFLAGS_smm) $(COMPILER_RT_FLAGS_smm) -o $(obj)/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld -Wl,--whole-archive,--start-group $(obj)/smm/smm.a -Wl,--no-whole-archive $(COMPILER_RT_smm) -Wl,--end-group $(NM_smm) -n $(obj)/smm/smm.elf | sort > $(obj)/smm/smm.map $(OBJCOPY_smm) -O binary $(obj)/smm/smm.elf $@ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index adcd16a..768331b 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -290,7 +290,7 @@ # rmdoule is named $(1).rmod define rmodule_link $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(call src-to-obj,rmodules_$(4),src/lib/rmodule.ld) | $$(RMODTOOL) - $$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(call src-to-obj,rmodules_$(4),src/lib/rmodule.ld) -Wl,--defsym=__heap_size=$(strip $(3)) -o $$@ -Wl,--whole-archive,--start-group $(filter-out %.ld,$(2)) -Wl,--end-group + $$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $$(COMPILER_RT_FLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(call src-to-obj,rmodules_$(4),src/lib/rmodule.ld) -Wl,--defsym=__heap_size=$(strip $(3)) -o $$@ -Wl,--whole-archive,--start-group $(filter-out %.ld,$(2)) -Wl,--no-whole-archive $$(COMPILER_RT_rmodules_$(4)) -Wl,--end-group $$(NM_rmodules_$(4)) -n $$@ > $$(basename $$(a)).map endef -- To view, visit https://review.coreboot.org/c/coreboot/+/40812 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I122a4542d1e98d89545897d5177c93ee463d0cdb Gerrit-Change-Number: 40812 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: nb/intel/haswell: Add RMRR for USB devices
by Angel Pons (Code Review) 03 May '22

03 May '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43807 ) Change subject: nb/intel/haswell: Add RMRR for USB devices ...................................................................... nb/intel/haswell: Add RMRR for USB devices FIXME: Figure out which address the RMRR corresponds to. VT-d checklist verifies that there's a RMRR entry for USB devices. If said devices are enabled, add the RMRR entry. Tested on Asrock B85M Pro4, verify VT-d check about USB RMRR passes. Change-Id: I800d6d1847f457827d64b39c5b7bbfc9cb04f230 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/acpi.c M src/southbridge/intel/lynxpoint/acpi.c M src/southbridge/intel/lynxpoint/pch.h 3 files changed, 36 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/43807/1 diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 6a6a124..5e28c82 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -87,7 +87,7 @@ acpi_dmar_drhd_fixup(tmp, current); } - return current; + return acpi_create_usb_rmrr(current); } unsigned long northbridge_write_acpi_tables(const struct device *const dev, diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index 8fee16b..6a2103b 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -77,3 +77,36 @@ ssdt->length = current - (unsigned long)ssdt; ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); } + +unsigned long acpi_create_usb_rmrr(const unsigned long tmp) +{ + unsigned long current = tmp; + + struct device *const ehc1_dev = pcidev_on_root(0x1d, 0); + struct device *const ehc2_dev = pcidev_on_root(0x1a, 0); + struct device *const xhci_dev = pcidev_on_root(0x14, 0); + + const bool ehc1_enabled = ehc1_dev && ehc1_dev->enabled; + const bool ehc2_enabled = ehc2_dev && ehc2_dev->enabled; + const bool xhci_enabled = xhci_dev && xhci_dev->enabled; + + /* If no USB devices are enabled, do not generate the RMRR entry */ + if (!ehc1_enabled && !ehc2_enabled && !xhci_enabled) + return current; + + /* FIXME: This should be the address of the runtime register space instead! */ + current += acpi_create_dmar_rmrr(current, 0, 0x3e2e0000, 0x3e300000 - 1); + + if (ehc1_enabled) + current += acpi_create_dmar_ds_pci(current, 0, 0x1d, 0); + + if (ehc2_enabled) + current += acpi_create_dmar_ds_pci(current, 0, 0x1a, 0); + + if (xhci_enabled) + current += acpi_create_dmar_ds_pci(current, 0, 0x14, 0); + + acpi_dmar_rmrr_fixup(tmp, current); + + return current; +} diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 9946944..79d9dbc 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -122,6 +122,8 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); +unsigned long acpi_create_usb_rmrr(const unsigned long tmp); + void enable_usb_bar(void); int early_pch_init(void); void pch_enable_lpc(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/43807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I800d6d1847f457827d64b39c5b7bbfc9cb04f230 Gerrit-Change-Number: 43807 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: haswell: Report only one HPET timer device
by Angel Pons (Code Review) 03 May '22

03 May '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43806 ) Change subject: haswell: Report only one HPET timer device ...................................................................... haswell: Report only one HPET timer device VT-d checklist fails if there are multiple devices for a single HPET timer block, and if the bus/dev/fn differs between HPET devices. Tested on Asrock B85M Pro4, verify VT-d check about HPET is successful. Change-Id: I68fd074f5440c634ff3ed28c5d423835c81d33b9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/acpi.c M src/southbridge/intel/lynxpoint/lpc.c 2 files changed, 4 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/43806/1 diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 1df66bc..6a6a124 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -82,10 +82,8 @@ current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); - size_t i; - for (i = 0; i < 8; ++i) - current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS, - PCH_HPET_PCI_SLOT, i); + current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS, + PCH_HPET_PCI_SLOT, 0); acpi_dmar_drhd_fixup(tmp, current); } diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 85fab4d..93b45d0 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -370,10 +370,10 @@ u32 reg32; size_t i; - /* Assign unique bus/dev/fn for each HPET */ + /* Assign the same bus/dev/fn for each HPET */ for (i = 0; i < 8; ++i) pci_write_config16(dev, LPC_HnBDF(i), - PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i); + PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | 0); /* Move HPET to default address 0xfed00000 and enable it */ reg32 = RCBA32(HPTC); -- To view, visit https://review.coreboot.org/c/coreboot/+/43806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68fd074f5440c634ff3ed28c5d423835c81d33b9 Gerrit-Change-Number: 43806 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: mb/lenovo/{t420,t420s}: Convert to variant board
by Peter Lemenkov (Code Review) 02 May '22

02 May '22

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40381 ) Change subject: mb/lenovo/{t420,t420s}: Convert to variant board ...................................................................... mb/lenovo/{t420,t420s}: Convert to variant board Change-Id: If117c48cf8e6131b3d25112346d4ddd1ff366009 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420/Kconfig.name M src/mainboard/lenovo/t420/Makefile.inc M src/mainboard/lenovo/t420/board_info.txt M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420/early_init.c M src/mainboard/lenovo/t420/gma-mainboard.ads M src/mainboard/lenovo/t420/hda_verb.c A src/mainboard/lenovo/t420/variants/t420/board_info.txt R src/mainboard/lenovo/t420/variants/t420/data.vbt A src/mainboard/lenovo/t420/variants/t420/early_init.c R src/mainboard/lenovo/t420/variants/t420/gpio.c A src/mainboard/lenovo/t420/variants/t420/hda_verb.c A src/mainboard/lenovo/t420/variants/t420/overridetree.cb R src/mainboard/lenovo/t420/variants/t420s/board_info.txt R src/mainboard/lenovo/t420/variants/t420s/data.vbt A src/mainboard/lenovo/t420/variants/t420s/early_init.c R src/mainboard/lenovo/t420/variants/t420s/gpio.c R src/mainboard/lenovo/t420/variants/t420s/hda_verb.c A src/mainboard/lenovo/t420/variants/t420s/overridetree.cb D src/mainboard/lenovo/t420s/Kconfig D src/mainboard/lenovo/t420s/Kconfig.name D src/mainboard/lenovo/t420s/Makefile.inc D src/mainboard/lenovo/t420s/acpi/ec.asl D src/mainboard/lenovo/t420s/acpi/platform.asl D src/mainboard/lenovo/t420s/acpi/superio.asl D src/mainboard/lenovo/t420s/acpi_tables.c D src/mainboard/lenovo/t420s/cmos.default D src/mainboard/lenovo/t420s/cmos.layout D src/mainboard/lenovo/t420s/devicetree.cb D src/mainboard/lenovo/t420s/dsdt.asl D src/mainboard/lenovo/t420s/early_init.c D src/mainboard/lenovo/t420s/gma-mainboard.ads D src/mainboard/lenovo/t420s/mainboard.c D src/mainboard/lenovo/t420s/smihandler.c D src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd D src/mainboard/lenovo/t420s/vboot-ro.fmd D src/mainboard/lenovo/t420s/vboot-rwa.fmd 38 files changed, 150 insertions(+), 853 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/40381/1 diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index dfc8ed1..b0523f6 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_T420 +if BOARD_LENOVO_T420 || BOARD_LENOVO_T420S config BOARD_SPECIFIC_OPTIONS def_bool y @@ -16,7 +16,7 @@ select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select INTEL_INT15 - select DRIVERS_RICOH_RCE822 + select DRIVERS_RICOH_RCE822 if BOARD_LENOVO_T420 select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select MAINBOARD_HAS_LIBGFXINIT @@ -51,9 +51,19 @@ string default "lenovo/t420" +config VARIANT_DIR + string + default "t420" if BOARD_LENOVO_T420 + default "t420s" if BOARD_LENOVO_T420S + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + config MAINBOARD_PART_NUMBER string - default "ThinkPad T420" + default "ThinkPad T420" if BOARD_LENOVO_T420 + default "ThinkPad T420s" if BOARD_LENOVO_T420S config MAX_CPUS int @@ -81,4 +91,4 @@ config PS2M_EISAID default "LEN0015" -endif # BOARD_LENOVO_T420 +endif # BOARD_LENOVO_T420 || BOARD_LENOVO_T420S diff --git a/src/mainboard/lenovo/t420/Kconfig.name b/src/mainboard/lenovo/t420/Kconfig.name index 75570ad..c43ec9d 100644 --- a/src/mainboard/lenovo/t420/Kconfig.name +++ b/src/mainboard/lenovo/t420/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_LENOVO_T420 bool "ThinkPad T420" + +config BOARD_LENOVO_T420S + bool "ThinkPad T420s" diff --git a/src/mainboard/lenovo/t420/Makefile.inc b/src/mainboard/lenovo/t420/Makefile.inc index 05befdd..df5ca02 100644 --- a/src/mainboard/lenovo/t420/Makefile.inc +++ b/src/mainboard/lenovo/t420/Makefile.inc @@ -15,7 +15,9 @@ smm-y += smihandler.c bootblock-y += gpio.c romstage-y += gpio.c - +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += variants/$(VARIANT_DIR)/early_init.c bootblock-y += early_init.c +romstage-y += variants/$(VARIANT_DIR)/early_init.c romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t420/board_info.txt b/src/mainboard/lenovo/t420/board_info.txt index c0f04ca..05146ff 100644 --- a/src/mainboard/lenovo/t420/board_info.txt +++ b/src/mainboard/lenovo/t420/board_info.txt @@ -1,3 +1,5 @@ +Vendor name: Lenovo +Board name: ThinkPad T420 baseboard Category: laptop ROM package: SOIC-8 / WSON-8 ROM protocol: SPI diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 5ac9cf5..ec4a57a 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -82,13 +82,7 @@ device pci 1c.3 on smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 ExpressCard - device pci 1c.4 on - chip drivers/ricoh/rce822 - register "sdwppol" = "1" - register "disable_mask" = "0x87" - device pci 00.0 on end - end - end # PCIe Port #5 (Ricoh SD & FW) + device pci 1c.4 on end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) device pci 1c.6 off end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 diff --git a/src/mainboard/lenovo/t420/early_init.c b/src/mainboard/lenovo/t420/early_init.c index 6c189f4..7a06bf0 100644 --- a/src/mainboard/lenovo/t420/early_init.c +++ b/src/mainboard/lenovo/t420/early_init.c @@ -34,24 +34,6 @@ pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -// OC3 set in BIOS to port 2-7, OC7 set in BIOS to port 10-13 -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, /* P0: system port 4, OC0 */ - { 1, 1, 1 }, /* P1: system port 2 (EHCI debug), OC 1 */ - { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ - { 1, 0, -1 }, /* P3: WWAN, no OC */ - { 1, 0, -1 }, /* P4: smartcard, no OC */ - { 1, 1, -1 }, /* P5: ExpressCard, no OC */ - { 0, 0, -1 }, /* P6: empty */ - { 0, 0, -1 }, /* P7: empty */ - { 1, 1, 4 }, /* P8: system port 3, OC4*/ - { 1, 1, 5 }, /* P9: system port 1 (EHCI debug), OC 5 */ - { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ - { 1, 0, -1 }, /* P11: bluetooth, no OC. */ - { 1, 1, -1 }, /* P12: docking, no OC */ - { 1, 1, -1 }, /* P13: camera (LCD), no OC */ -}; - void mainboard_get_spd(spd_raw_data *spd, bool id_only) { read_spd(&spd[0], 0x50, id_only); diff --git a/src/mainboard/lenovo/t420/gma-mainboard.ads b/src/mainboard/lenovo/t420/gma-mainboard.ads index a26b993..fae3544 100644 --- a/src/mainboard/lenovo/t420/gma-mainboard.ads +++ b/src/mainboard/lenovo/t420/gma-mainboard.ads @@ -1,4 +1,4 @@ --- SPDX-License-Identifier: GPL-2.0-only +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. with HW.GFX.GMA; diff --git a/src/mainboard/lenovo/t420/hda_verb.c b/src/mainboard/lenovo/t420/hda_verb.c index 690c936..2997587 100644 --- a/src/mainboard/lenovo/t420/hda_verb.c +++ b/src/mainboard/lenovo/t420/hda_verb.c @@ -1,45 +1 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -/* Bits 31:28 - Codec Address */ -/* Bits 27:20 - NID */ -/* Bits 19:8 - Verb ID */ -/* Bits 7:0 - Payload */ - -#include <device/azalia_device.h> - -const u32 cim_verb_data[] = { - 0x14f1506e, /* Codec VID / DID: Conexant CX20590 - schematic shows CX20672 */ - 0x17aa21ce, /* Subsystem ID */ - 13, /* Number of 4 dword sets */ - AZALIA_SUBVENDOR(0, 0x17aa21d2), - AZALIA_PIN_CFG(0, 0x12, 0x90a60140), - AZALIA_PIN_CFG(0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0, 0x15, 0x03211020), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x03a11830), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1d, 0x40138205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), - - /* Misc entries */ - 0x00b707C0, /* Enable PortB as Output with HP amp */ - 0x00d70740, /* Enable PortD as Output */ - 0x0017a200, /* Disable ClkEn of PortSenseTst */ - 0x0017c621, /* Slave Port - Port A used as microphone input for - combo Jack - Master Port - Port B used for Jack Presence Detect - Enable Combo Jack Detection */ - 0x0017a208, /* Enable ClkEn of PortSenseTst */ - 0x00170500, /* Set power state to D0 */ - 0x00170500, /* Padding */ - 0x00170500, /* Padding */ -}; - -const u32 pc_beep_verbs[] = { - 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */ -}; - -AZALIA_ARRAY_SIZES; +/* dummy */ diff --git a/src/mainboard/lenovo/t420/variants/t420/board_info.txt b/src/mainboard/lenovo/t420/variants/t420/board_info.txt new file mode 100644 index 0000000..c0f04ca --- /dev/null +++ b/src/mainboard/lenovo/t420/variants/t420/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM package: SOIC-8 / WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2011 diff --git a/src/mainboard/lenovo/t420/data.vbt b/src/mainboard/lenovo/t420/variants/t420/data.vbt similarity index 100% rename from src/mainboard/lenovo/t420/data.vbt rename to src/mainboard/lenovo/t420/variants/t420/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/t420/variants/t420/early_init.c b/src/mainboard/lenovo/t420/variants/t420/early_init.c new file mode 100644 index 0000000..4b71060 --- /dev/null +++ b/src/mainboard/lenovo/t420/variants/t420/early_init.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <southbridge/intel/bd82x6x/pch.h> + +// OC3 set in BIOS to port 2-7, OC7 set in BIOS to port 10-13 +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, /* P0: system port 4, OC0 */ + { 1, 1, 1 }, /* P1: system port 2 (EHCI debug), OC 1 */ + { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ + { 1, 0, -1 }, /* P3: WWAN, no OC */ + { 1, 0, -1 }, /* P4: smartcard, no OC */ + { 1, 1, -1 }, /* P5: ExpressCard, no OC */ + { 0, 0, -1 }, /* P6: empty */ + { 0, 0, -1 }, /* P7: empty */ + { 1, 1, 4 }, /* P8: system port 3, OC4*/ + { 1, 1, 5 }, /* P9: system port 1 (EHCI debug), OC 5 */ + { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ + { 1, 0, -1 }, /* P11: bluetooth, no OC. */ + { 1, 1, -1 }, /* P12: docking, no OC */ + { 1, 1, -1 }, /* P13: camera (LCD), no OC */ +}; diff --git a/src/mainboard/lenovo/t420/gpio.c b/src/mainboard/lenovo/t420/variants/t420/gpio.c similarity index 100% rename from src/mainboard/lenovo/t420/gpio.c rename to src/mainboard/lenovo/t420/variants/t420/gpio.c diff --git a/src/mainboard/lenovo/t420/variants/t420/hda_verb.c b/src/mainboard/lenovo/t420/variants/t420/hda_verb.c new file mode 100644 index 0000000..690c936 --- /dev/null +++ b/src/mainboard/lenovo/t420/variants/t420/hda_verb.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* Bits 31:28 - Codec Address */ +/* Bits 27:20 - NID */ +/* Bits 19:8 - Verb ID */ +/* Bits 7:0 - Payload */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x14f1506e, /* Codec VID / DID: Conexant CX20590 - schematic shows CX20672 */ + 0x17aa21ce, /* Subsystem ID */ + 13, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x17aa21d2), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x03211020), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x03a11830), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40138205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + /* Misc entries */ + 0x00b707C0, /* Enable PortB as Output with HP amp */ + 0x00d70740, /* Enable PortD as Output */ + 0x0017a200, /* Disable ClkEn of PortSenseTst */ + 0x0017c621, /* Slave Port - Port A used as microphone input for + combo Jack + Master Port - Port B used for Jack Presence Detect + Enable Combo Jack Detection */ + 0x0017a208, /* Enable ClkEn of PortSenseTst */ + 0x00170500, /* Set power state to D0 */ + 0x00170500, /* Padding */ + 0x00170500, /* Padding */ +}; + +const u32 pc_beep_verbs[] = { + 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */ +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/t420/variants/t420/overridetree.cb b/src/mainboard/lenovo/t420/variants/t420/overridetree.cb new file mode 100644 index 0000000..c0b503c --- /dev/null +++ b/src/mainboard/lenovo/t420/variants/t420/overridetree.cb @@ -0,0 +1,13 @@ +chip northbridge/intel/sandybridge + device domain 0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + device pci 1c.4 on + chip drivers/ricoh/rce822 + register "sdwppol" = "1" + register "disable_mask" = "0x87" + device pci 00.0 on end + end + end # PCIe Port #5 (Ricoh SD & FW) + end + end +end diff --git a/src/mainboard/lenovo/t420s/board_info.txt b/src/mainboard/lenovo/t420/variants/t420s/board_info.txt similarity index 100% rename from src/mainboard/lenovo/t420s/board_info.txt rename to src/mainboard/lenovo/t420/variants/t420s/board_info.txt diff --git a/src/mainboard/lenovo/t420s/data.vbt b/src/mainboard/lenovo/t420/variants/t420s/data.vbt similarity index 100% rename from src/mainboard/lenovo/t420s/data.vbt rename to src/mainboard/lenovo/t420/variants/t420s/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/t420/variants/t420s/early_init.c b/src/mainboard/lenovo/t420/variants/t420s/early_init.c new file mode 100644 index 0000000..3066da5 --- /dev/null +++ b/src/mainboard/lenovo/t420/variants/t420s/early_init.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 0, 1, -1 }, /* P0: empty */ + { 1, 1, 1 }, /* P1: system port 2 (To system port) (EHCI debug), OC 1 */ + { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ + { 1, 0, -1 }, /* P3: WWAN, no OC */ + { 1, 1, -1 }, /* P4: smartcard, no OC */ + { 1, 1, -1 }, /* P5: ExpressCard, no OC */ + { 0, 0, -1 }, /* P6: empty */ + { 0, 0, -1 }, /* P7: empty */ + { 0, 1, -1 }, /* P8: empty (touch panel) */ + { 1, 0, 5 }, /* P9: system port 1 (To USBAO) (EHCI debug), OC 5 */ + { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ + { 1, 1, -1 }, /* P11: bluetooth, no OC. */ + { 1, 1, -1 }, /* P12: docking, no OC */ + { 1, 1, -1 }, /* P13: camera (LCD), no OC */ +}; diff --git a/src/mainboard/lenovo/t420s/gpio.c b/src/mainboard/lenovo/t420/variants/t420s/gpio.c similarity index 100% rename from src/mainboard/lenovo/t420s/gpio.c rename to src/mainboard/lenovo/t420/variants/t420s/gpio.c diff --git a/src/mainboard/lenovo/t420s/hda_verb.c b/src/mainboard/lenovo/t420/variants/t420s/hda_verb.c similarity index 100% rename from src/mainboard/lenovo/t420s/hda_verb.c rename to src/mainboard/lenovo/t420/variants/t420s/hda_verb.c diff --git a/src/mainboard/lenovo/t420/variants/t420s/overridetree.cb b/src/mainboard/lenovo/t420/variants/t420s/overridetree.cb new file mode 100644 index 0000000..e12d7ea --- /dev/null +++ b/src/mainboard/lenovo/t420/variants/t420s/overridetree.cb @@ -0,0 +1,18 @@ +chip northbridge/intel/sandybridge + device domain 0 on + subsystemid 0x17aa 0x21d2 inherit + + device pci 02.0 on + subsystemid 0x17aa 0x21d3 + end # Integrated Graphics Controller + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 4 (dock) + register "sata_port_map" = "0x17" + + device pci 19.0 on + subsystemid 0x17aa 0x21ce + end # Intel Gigabit Ethernet + end + end +end diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig deleted file mode 100644 index e2fd824..0000000 --- a/src/mainboard/lenovo/t420s/Kconfig +++ /dev/null @@ -1,83 +0,0 @@ -if BOARD_LENOVO_T420S - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_SANDYBRIDGE - select USE_NATIVE_RAMINIT - select SOUTHBRIDGE_INTEL_BD82X6X - select EC_LENOVO_PMH7 - select EC_LENOVO_H8 - select H8_HAS_BAT_TRESHOLDS_IMPL - select NO_UART_ON_SUPERIO - select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_CMOS_DEFAULT - select HAVE_ACPI_RESUME - select INTEL_INT15 - select MAINBOARD_HAS_LPC_TPM - select MAINBOARD_HAS_TPM1 - select MAINBOARD_HAS_LIBGFXINIT - select GFX_GMA_PANEL_1_ON_LVDS - select DRIVERS_LENOVO_HYBRID_GRAPHICS - select INTEL_GMA_HAVE_VBT - select MAINBOARD_USES_IFD_GBE_REGION - - # Workaround for EC/KBC IRQ1. - select SERIRQ_CONTINUOUS_MODE - -config VBOOT - select VBOOT_VBNV_CMOS - select GBB_FLAG_DISABLE_LID_SHUTDOWN - select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC - select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC - select GBB_FLAG_DISABLE_FWMP - select HAS_RECOVERY_MRC_CACHE - -config VBOOT_SLOTS_RW_A - default y - -config VBOOT_VBNV_OFFSET - hex - default 0x2a - -config FMDFILE - string - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT - -config MAINBOARD_DIR - string - default "lenovo/t420s" - -config MAINBOARD_PART_NUMBER - string - default "ThinkPad T420s" - -config MAX_CPUS - int - default 8 - -config USBDEBUG_HCD_INDEX - int - default 2 - -config DRAM_RESET_GATE_GPIO - int - default 10 - -config VGA_BIOS_FILE - string - default "pci8086,0126.rom" - -config VGA_BIOS_ID - string - default "8086,0126" - -config PS2K_EISAID - default "PNP0303" - -config PS2M_EISAID - default "LEN0015" - -endif # BOARD_LENOVO_T420S diff --git a/src/mainboard/lenovo/t420s/Kconfig.name b/src/mainboard/lenovo/t420s/Kconfig.name deleted file mode 100644 index 648688b..0000000 --- a/src/mainboard/lenovo/t420s/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_LENOVO_T420S - bool "ThinkPad T420s" diff --git a/src/mainboard/lenovo/t420s/Makefile.inc b/src/mainboard/lenovo/t420s/Makefile.inc deleted file mode 100644 index 05befdd..0000000 --- a/src/mainboard/lenovo/t420s/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -smm-y += smihandler.c -bootblock-y += gpio.c -romstage-y += gpio.c - -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -bootblock-y += early_init.c -romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t420s/acpi/ec.asl b/src/mainboard/lenovo/t420s/acpi/ec.asl deleted file mode 100644 index 2dda5ec..0000000 --- a/src/mainboard/lenovo/t420s/acpi/ec.asl +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <ec/lenovo/h8/acpi/ec.asl> - -Scope(\_SB.PCI0.LPCB.EC) -{ -} - -#include <ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl> diff --git a/src/mainboard/lenovo/t420s/acpi/platform.asl b/src/mainboard/lenovo/t420s/acpi/platform.asl deleted file mode 100644 index dc46182..0000000 --- a/src/mainboard/lenovo/t420s/acpi/platform.asl +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ - \_SB.PCI0.LPCB.EC.MUTE(1) - \_SB.PCI0.LPCB.EC.USBP(0) - \_SB.PCI0.LPCB.EC.RADI(0) -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - /* ME may not be up yet. */ - Store (0, \_TZ.MEB1) - Store (0, \_TZ.MEB2) - - /* Wake the HKEY to init BT/WWAN */ - \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) - - /* Not implemented. */ - Return(Package(){0,0}) -} diff --git a/src/mainboard/lenovo/t420s/acpi/superio.asl b/src/mainboard/lenovo/t420s/acpi/superio.asl deleted file mode 100644 index f2b35ba..0000000 --- a/src/mainboard/lenovo/t420s/acpi/superio.asl +++ /dev/null @@ -1 +0,0 @@ -#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/t420s/acpi_tables.c b/src/mainboard/lenovo/t420s/acpi_tables.c deleted file mode 100644 index 65c6019..0000000 --- a/src/mainboard/lenovo/t420s/acpi_tables.c +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <southbridge/intel/bd82x6x/nvs.h> - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - /* The lid is open by default */ - gnvs->lids = 1; - - /* Temperature at which OS will shutdown */ - gnvs->tcrt = 100; - /* Temperature at which OS will throttle CPU */ - gnvs->tpsv = 90; -} diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default deleted file mode 100644 index 467f965..0000000 --- a/src/mainboard/lenovo/t420s/cmos.default +++ /dev/null @@ -1,16 +0,0 @@ -boot_option=Fallback -debug_level=Debug -power_on_after_fail=Disable -nmi=Enable -volume=0x3 -first_battery=Primary -bluetooth=Enable -wwan=Enable -wlan=Enable -touchpad=Enable -sata_mode=AHCI -fn_ctrl_swap=Disable -sticky_fn=Disable -trackpoint=Enable -hybrid_graphics_mode=Integrated Only -usb_always_on=Disable diff --git a/src/mainboard/lenovo/t420s/cmos.layout b/src/mainboard/lenovo/t420s/cmos.layout deleted file mode 100644 index 26e6300..0000000 --- a/src/mainboard/lenovo/t420s/cmos.layout +++ /dev/null @@ -1,141 +0,0 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused - -#400 8 r 0 reserved for century byte - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail - -# coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 1 e 1 power_management_beeps -421 1 e 9 sata_mode -422 2 e 13 usb_always_on - -# coreboot config options: cpu -#424 8 r 0 unused - -# coreboot config options: northbridge -432 3 e 11 gfx_uma_size -435 2 e 12 hybrid_graphics_mode -#437 3 r 0 unused - -440 8 h 0 volume - -# VBOOT -448 128 r 0 vbnv - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk - -# coreboot config options: check sums -984 16 h 0 check_sum - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 Both -10 1 Keyboard only -10 2 Thinklight only -10 3 None -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M -12 0 Integrated Only -12 1 Discrete Only -12 2 Dual Graphics -13 0 Disable -13 1 AC and battery -13 2 AC only - -# ----------------------------------------------------------------- -checksums - -checksum 392 447 984 diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb deleted file mode 100644 index b3399c3..0000000 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ /dev/null @@ -1,175 +0,0 @@ -chip northbridge/intel/sandybridge - # IGD Displays - register "gfx" = "GMA_STATIC_DISPLAYS(1)" - - # Enable DisplayPort Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS - register "gpu_panel_power_cycle_delay" = "1" - register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms - register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms - register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms - register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x06100610" - - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0x0 on end - device lapic 0xacac off end - - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) - end - end - - register "pci_mmio_size" = "2048" - - device domain 0 on - subsystemid 0x17aa 0x21d2 inherit - - device pci 00.0 on end # host bridge - device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] - device pci 02.0 on - subsystemid 0x17aa 0x21d3 - end # Integrated Graphics Controller - - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) - register "alt_gp_smi_en" = "0x0000" - register "gpi1_routing" = "2" - register "gpi13_routing" = "2" - - # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 4 (dock) - register "sata_port_map" = "0x17" - # Set max SATA speed to 6.0 Gb/s - register "sata_interface_speed_support" = "0x3" - - register "gen1_dec" = "0x7c1601" - register "gen2_dec" = "0x0c15e1" - register "gen4_dec" = "0x0c06a1" - - register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" - - # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" - - register "c2_latency" = "101" # c2 not supported - - # device specific SPI configuration - register "spi_uvscc" = "0x2005" - register "spi_lvscc" = "0x2005" - - device pci 16.0 off end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on - subsystemid 0x17aa 0x21ce - end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB Enhanced Host Controller #2 - device pci 1b.0 on end # High Definition Audio Controller - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on - smbios_slot_desc "7" "3" "ExpressCard Slot" "8" - end # PCIe Port #4 ExpressCard - device pci 1c.4 on end # PCIe Port #5 NEC Corporation uPD720200A USB 3.0 Host Controller - device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB Enhanced Host Controller #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip ec/lenovo/pmh7 - device pnp ff.1 on end # dummy - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" - end - - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - - chip ec/lenovo/h8 - device pnp ff.2 on # dummy - io 0x60 = 0x62 - io 0x62 = 0x66 - io 0x64 = 0x1600 - io 0x66 = 0x1604 - end - - register "config0" = "0xa7" - register "config1" = "0x01" - register "config2" = "0xa0" - register "config3" = "0xe2" - - register "has_keyboard_backlight" = "0" - - register "beepmask0" = "0x02" - register "beepmask1" = "0x86" - register "has_power_management_beeps" = "1" - register "event2_enable" = "0xff" - register "event3_enable" = "0xff" - register "event4_enable" = "0xf0" - register "event5_enable" = "0x3c" - register "event6_enable" = "0x00" - register "event7_enable" = "0xa1" - register "event8_enable" = "0x7b" - register "event9_enable" = "0xff" - register "eventa_enable" = "0x00" - register "eventb_enable" = "0x00" - register "eventc_enable" = "0xff" - register "eventd_enable" = "0xff" - register "evente_enable" = "0x0d" - - register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "54" - register "bdc_gpio_lvl" = "0" - end - chip drivers/lenovo/hybrid_graphics - device pnp ff.f on end # dummy - - register "detect_gpio" = "21" - - register "has_panel_hybrid_gpio" = "1" - register "panel_hybrid_gpio" = "52" - register "panel_integrated_lvl" = "1" - - register "has_backlight_gpio" = "0" - register "has_dgpu_power_gpio" = "0" - - register "has_thinker1" = "1" - end - end # LPC Controller - device pci 1f.2 on end # 6 port SATA AHCI Controller - device pci 1f.3 on - # eeprom, 8 virtual devices, same chip - chip drivers/i2c/at24rf08c - device i2c 54 on end - device i2c 55 on end - device i2c 56 on end - device i2c 57 on end - device i2c 5c on end - device i2c 5d on end - device i2c 5e on end - device i2c 5f on end - end - end # SMBus Controller - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal - end - end -end diff --git a/src/mainboard/lenovo/t420s/dsdt.asl b/src/mainboard/lenovo/t420s/dsdt.asl deleted file mode 100644 index a03b252..0000000 --- a/src/mainboard/lenovo/t420s/dsdt.asl +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#define THINKPAD_EC_GPE 17 -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#define EC_LENOVO_H8_ME_WORKAROUND 1 - -#include <arch/acpi.h> -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 // OEM revision -) -{ - #include <southbridge/intel/common/acpi/platform.asl> - - #include "acpi/platform.asl" - - // global NVS and variables - #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - - #include <cpu/intel/common/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <southbridge/intel/bd82x6x/acpi/pch.asl> - - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - } - } - - #include <southbridge/intel/common/acpi/sleepstates.asl> -} diff --git a/src/mainboard/lenovo/t420s/early_init.c b/src/mainboard/lenovo/t420s/early_init.c deleted file mode 100644 index 4f5f69d..0000000 --- a/src/mainboard/lenovo/t420s/early_init.c +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <device/pci_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> -#include <northbridge/intel/sandybridge/sandybridge.h> -#include <device/device.h> - -static void hybrid_graphics_init(void) -{ - bool peg, igd; - u32 reg32; - - early_hybrid_graphics(&igd, &peg); - - if (peg && igd) - return; - - /* Hide disabled devices */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); - reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); - - if (peg) - reg32 |= DEVEN_PEG10; - - if (igd) - reg32 |= DEVEN_IGD; - else - /* Disable IGD VGA decode, no GTT or GFX stolen */ - pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); - - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); -} - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 0, 1, -1 }, /* P0: empty */ - { 1, 1, 1 }, /* P1: system port 2 (To system port) (EHCI debug), OC 1 */ - { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ - { 1, 0, -1 }, /* P3: WWAN, no OC */ - { 1, 1, -1 }, /* P4: smartcard, no OC */ - { 1, 1, -1 }, /* P5: ExpressCard, no OC */ - { 0, 0, -1 }, /* P6: empty */ - { 0, 0, -1 }, /* P7: empty */ - { 0, 1, -1 }, /* P8: empty (touch panel) */ - { 1, 0, 5 }, /* P9: system port 1 (To USBAO) (EHCI debug), OC 5 */ - { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ - { 1, 1, -1 }, /* P11: bluetooth, no OC. */ - { 1, 1, -1 }, /* P12: docking, no OC */ - { 1, 1, -1 }, /* P13: camera (LCD), no OC */ -}; - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x51, id_only); -} - -void mainboard_early_init(int s3resume) -{ - hybrid_graphics_init(); -} diff --git a/src/mainboard/lenovo/t420s/gma-mainboard.ads b/src/mainboard/lenovo/t420s/gma-mainboard.ads deleted file mode 100644 index fae3544..0000000 --- a/src/mainboard/lenovo/t420s/gma-mainboard.ads +++ /dev/null @@ -1,23 +0,0 @@ --- SPDX-License-Identifier: GPL-2.0-or-later --- This file is part of the coreboot project. - -with HW.GFX.GMA; -with HW.GFX.GMA.Display_Probing; - -use HW.GFX.GMA; -use HW.GFX.GMA.Display_Probing; - -private package GMA.Mainboard is - - ports : constant Port_List := - (DP1, - DP2, - DP3, - HDMI1, - HDMI2, - HDMI3, - Analog, - LVDS, - others => Disabled); - -end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t420s/mainboard.c b/src/mainboard/lenovo/t420s/mainboard.c deleted file mode 100644 index 0890151..0000000 --- a/src/mainboard/lenovo/t420s/mainboard.c +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <device/device.h> -#include <drivers/intel/gma/int15.h> -#include <ec/lenovo/h8/h8.h> - -static void mainboard_enable(struct device *dev) -{ - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, - GMA_INT15_PANEL_FIT_DEFAULT, - GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/lenovo/t420s/smihandler.c b/src/mainboard/lenovo/t420s/smihandler.c deleted file mode 100644 index 4432995..0000000 --- a/src/mainboard/lenovo/t420s/smihandler.c +++ /dev/null @@ -1,69 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <ec/acpi/ec.h> -#include <ec/lenovo/h8/h8.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/common/pmutil.h> - -#define GPE_EC_SCI 1 -#define GPE_EC_WAKE 13 - -static void mainboard_smi_handle_ec_sci(void) -{ - u8 status = inb(EC_SC); - u8 event; - - if (!(status & EC_SCI_EVT)) - return; - - event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); -} - -void mainboard_smi_gpi(u32 gpi_sts) -{ - if (gpi_sts & (1 << GPE_EC_SCI)) - mainboard_smi_handle_ec_sci(); -} - -int mainboard_smi_apmc(u8 data) -{ - switch (data) { - case APM_CNT_ACPI_ENABLE: - /* use 0x1600/0x1604 to prevent races with userspace */ - ec_set_ports(0x1604, 0x1600); - /* route EC_SCI to SCI */ - gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); - /* discard all events, and enable attention */ - ec_write(0x80, 0x01); - break; - case APM_CNT_ACPI_DISABLE: - /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't - provide a EC query function */ - ec_set_ports(0x66, 0x62); - /* route EC_SCI to SMI */ - gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); - /* discard all events, and enable attention */ - ec_write(0x80, 0x01); - break; - default: - break; - } - return 0; -} - -void mainboard_smi_sleep(u8 slp_typ) -{ - if (slp_typ == 3) { - u8 ec_wake = ec_read(0x32); - /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ - if (ec_wake & 0x14) { - /* Redirect EC WAKE GPE to SCI. */ - gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); - } - } -} diff --git a/src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd deleted file mode 100644 index d1cbff7..0000000 --- a/src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd +++ /dev/null @@ -1,22 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL 0x20000 { - SI_DESC 0x1000 - SI_GBE 0x2000 - SI_ME - } - SI_BIOS 0x7e0000 { - UNIFIED_MRC_CACHE 0x20000 { - RECOVERY_MRC_CACHE 0x10000 - RW_MRC_CACHE 0x10000 - } - - WP_RO { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 - RO_VPD(PRESERVE) 0x1000 - GBB 0x1e000 - COREBOOT(CBFS) - } - } -} diff --git a/src/mainboard/lenovo/t420s/vboot-ro.fmd b/src/mainboard/lenovo/t420s/vboot-ro.fmd deleted file mode 100644 index 51df8a5..0000000 --- a/src/mainboard/lenovo/t420s/vboot-ro.fmd +++ /dev/null @@ -1,22 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL 0x500000 { - SI_DESC 0x1000 - SI_GBE 0x2000 - SI_ME 0x4ed000 - } - SI_BIOS 0x300000 { - UNIFIED_MRC_CACHE 0x20000 { - RECOVERY_MRC_CACHE 0x10000 - RW_MRC_CACHE 0x10000 - } - - WP_RO { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 - RO_VPD(PRESERVE) 0x1000 - GBB 0x1e000 - COREBOOT(CBFS) - } - } -} diff --git a/src/mainboard/lenovo/t420s/vboot-rwa.fmd b/src/mainboard/lenovo/t420s/vboot-rwa.fmd deleted file mode 100644 index 8a4cd3b..0000000 --- a/src/mainboard/lenovo/t420s/vboot-rwa.fmd +++ /dev/null @@ -1,29 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL@0x0 0x500000 { - SI_DESC@0x0 0x1000 - SI_GBE@0x1000 0x2000 - SI_ME@0x3000 0x4ed000 - } - SI_BIOS@0x500000 0x300000 { - RW_SECTION_A@0x00000 0x180000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x16ffc0 - RW_FWID_A@0x17ffc0 0x40 - } - UNIFIED_MRC_CACHE@0x180000 0x20000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 - } - RW_VPD(PRESERVE)@0x1a0000 0x1000 - SMMSTORE(PRESERVE)@0x1a1000 0x40000 - - WP_RO@0x1e1000 0x11f000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 - RO_VPD(PRESERVE)@0x1000 0x1000 - GBB@0x2000 0x1e000 - COREBOOT(CBFS)@0x20000 0xff000 - } - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/40381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If117c48cf8e6131b3d25112346d4ddd1ff366009 Gerrit-Change-Number: 40381 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: cpu/x86: Test the GNVS pointer before actually setting it
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47014 ) Change subject: cpu/x86: Test the GNVS pointer before actually setting it ...................................................................... cpu/x86: Test the GNVS pointer before actually setting it Change-Id: I15f67a12dbdd2529572eebf354cfbcf67017ca6d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/baytrail/smihandler.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/broadwell/pch/smihandler.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/denverton_ns/smihandler.c M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/ibexpeak/smihandler.c M src/southbridge/intel/lynxpoint/smihandler.c 8 files changed, 27 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/47014/1 diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 1810821..e1387b2 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -320,11 +320,12 @@ state = smi_apmc_find_state_save(reg8); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((uint32_t)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { + void *test_gnvs = (void *)((u32)state->rbx); + if (smm_points_to_smram(test_gnvs, sizeof(*gnvs))) { printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); return; } + gnvs = test_gnvs; smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index 6e250d8..e422777 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -299,11 +299,12 @@ state = smi_apmc_find_state_save(reg8); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((uint32_t)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { + void *test_gnvs = (void *)((u32)state->rbx); + if (smm_points_to_smram(test_gnvs, sizeof(*gnvs))) { printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); return; } + gnvs = test_gnvs; smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } diff --git a/src/soc/intel/broadwell/pch/smihandler.c b/src/soc/intel/broadwell/pch/smihandler.c index fd5d452..f3b0cd2 100644 --- a/src/soc/intel/broadwell/pch/smihandler.c +++ b/src/soc/intel/broadwell/pch/smihandler.c @@ -342,11 +342,12 @@ state = smi_apmc_find_state_save(reg8); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { + void *test_gnvs = (void *)((u32)state->rbx); + if (smm_points_to_smram(test_gnvs, sizeof(*gnvs))) { printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); return; } + gnvs = test_gnvs; smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 270b1aa..141f084 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -370,12 +370,12 @@ state = find_save_state(save_state_ops, reg8); if (state) { /* EBX in the state save contains the GNVS pointer */ - uint32_t reg_ebx = save_state_ops->get_reg(state, RBX); - gnvs = (struct global_nvs *)(uintptr_t)reg_ebx; - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { + void *test_gnvs = (void *)((u32)state->rbx); + if (smm_points_to_smram(test_gnvs, sizeof(*gnvs))) { printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); return; } + gnvs = test_gnvs; smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index 5eecba7..1e7d1e3 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -240,7 +240,12 @@ state = smi_apmc_find_state_save(reg8); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((uint32_t)state->rbx); + void *test_gnvs = (void *)((u32)state->rbx); + if (smm_points_to_smram(test_gnvs, sizeof(*gnvs))) { + printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); + return; + } + gnvs = test_gnvs; smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 40672f8..f390d06 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -191,12 +191,12 @@ smi_apmc_find_state_save(apm_cnt); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); - struct region r = {(uintptr_t)gnvs, sizeof(struct global_nvs)}; - if (smm_region_overlaps_handler(&r)) { + void *test_gnvs = (void *)((u32)state->rbx); + if (smm_points_to_smram(test_gnvs, sizeof(*gnvs))) { printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); return; } + gnvs = test_gnvs; *smm_done = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 0c5e954..e53705a 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -153,11 +153,12 @@ smi_apmc_find_state_save(apm_cnt); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)(uintptr_t)((u32)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { + void *test_gnvs = (void *)((u32)state->rbx); + if (smm_points_to_smram(test_gnvs, sizeof(*gnvs))) { printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); return; } + gnvs = test_gnvs; *smm_done = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 9a5e5c0..b6fe7bf 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -313,11 +313,12 @@ state = smi_apmc_find_state_save(reg8); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { + void *test_gnvs = (void *)((u32)state->rbx); + if (smm_points_to_smram(test_gnvs, sizeof(*gnvs))) { printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); return; } + gnvs = test_gnvs; smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15f67a12dbdd2529572eebf354cfbcf67017ca6d Gerrit-Change-Number: 47014 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/intel/soc: Remove save state handler code
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45477 ) Change subject: soc/intel/soc: Remove save state handler code ...................................................................... soc/intel/soc: Remove save state handler code Change-Id: I08349fd4f8d0a3dcd64f70ddfc9d18abcafb9d3b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/apollolake/smihandler.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/cannonlake/smihandler.c M src/soc/intel/common/block/include/intelblocks/smihandler.h M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/common/block/smm/smitraphandler.c M src/soc/intel/denverton_ns/smihandler.c M src/soc/intel/icelake/smihandler.c M src/soc/intel/jasperlake/smihandler.c M src/soc/intel/skylake/smihandler.c M src/soc/intel/tigerlake/smihandler.c M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/lynxpoint/smihandler.c 15 files changed, 54 insertions(+), 461 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/45477/1 diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c index bcbc819..ddde65d 100644 --- a/src/soc/intel/apollolake/smihandler.c +++ b/src/soc/intel/apollolake/smihandler.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <cpu/x86/smm.h> -#include <cpu/intel/em64t100_save_state.h> #include <intelblocks/smihandler.h> #include <soc/gpio.h> #include <soc/iomap.h> @@ -15,12 +14,7 @@ return 1; } -const struct smm_save_state_ops *get_smm_save_state_ops(void) -{ - return &em64t100_smm_ops; -} - -const smi_handler_t southbridge_smi[32] = { +const void (*southbridge_smi[32])(void) = { [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, [APM_STS_BIT] = smihandler_southbridge_apmc, [PM1_STS_BIT] = smihandler_southbridge_pm1, diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 9348ae0..0372e81 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -6,7 +6,7 @@ #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t100_save_state.h> +#include <cpu/x86/save_state.h> #include <device/pci_def.h> #include <elog.h> #include <halt.h> @@ -152,41 +152,6 @@ } /* - * Look for Synchronous IO SMI and use save state from that core in case - * we are not running on the same core that initiated the IO transaction. - */ -static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) -{ - em64t100_smm_state_save_area_t *state; - int node; - - /* Check all nodes looking for the one that issued the IO */ - for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0==1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4==0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - - /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) - continue; - - return state; - } - - return NULL; -} - -/* * soc_legacy: A payload (Depthcharge) has indicated that the * legacy payload (SeaBIOS) is being loaded. Switch devices that are * in ACPI mode to PCI mode so that non-ACPI drivers may work. @@ -278,11 +243,10 @@ printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); return; } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((uint32_t)state->rbx); - smm_initialized = 1; + int node = get_apmc_node(reg8); + if (node >= 0) { + if (!get_save_state_reg(RBX, node, &gnvs, sizeof(gnvs))) + smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index 6f8cd62..b9ba4d8 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -7,7 +7,7 @@ #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t100_save_state.h> +#include <cpu/x86/save_state.h> #include <device/pci_def.h> #include <elog.h> #include <soc/nvs.h> @@ -185,41 +185,6 @@ } } -/* - * Look for Synchronous IO SMI and use save state from that core in case - * we are not running on the same core that initiated the IO transaction. - */ -static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) -{ - em64t100_smm_state_save_area_t *state; - int node; - - /* Check all nodes looking for the one that issued the IO */ - for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0==1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4==0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - - /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) - continue; - - return state; - } - - return NULL; -} - static void southbridge_smi_apmc(void) { uint8_t reg8; @@ -258,11 +223,10 @@ printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); return; } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((uint32_t)state->rbx); - smm_initialized = 1; + int node = get_apmc_node(reg8); + if (node >= 0) { + if (!get_save_state_reg(RBX, node, &gnvs, sizeof(gnvs))) + smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index a223bf5..0ccdc5b 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -9,7 +9,7 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> +#include <cpu/x86/save_state.h> #include <spi-generic.h> #include <elog.h> #include <halt.h> @@ -231,46 +231,9 @@ } } -/* - * Look for Synchronous IO SMI and use save state from that - * core in case we are not running on the same core that - * initiated the IO transaction. - */ -static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) -{ - em64t101_smm_state_save_area_t *state; - int node; - - /* Check all nodes looking for the one that issued the IO */ - for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0==1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4==0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - - /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) - continue; - - return state; - } - - return NULL; -} - static void southbridge_smi_apmc(void) { u8 reg8; - em64t101_smm_state_save_area_t *state; /* Emulate B2 register as the FADT / Linux expects it */ @@ -296,11 +259,10 @@ "SMI#: SMM structures already initialized!\n"); return; } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); - smm_initialized = 1; + int node = get_apmc_node(reg8); + if (node >= 0) { + if (!get_save_state_reg(RBX, node, &gnvs, sizeof(gnvs))) + smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index 266c258..4ba142e 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -25,7 +25,7 @@ heci_disable(); } -const smi_handler_t southbridge_smi[SMI_STS_BITS] = { +const void (*southbridge_smi[SMI_STS_BITS])(void) = { [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, [APM_STS_BIT] = smihandler_southbridge_apmc, [PM1_STS_BIT] = smihandler_southbridge_pm1, diff --git a/src/soc/intel/common/block/include/intelblocks/smihandler.h b/src/soc/intel/common/block/include/intelblocks/smihandler.h index 7cea1dd..7ebd31c 100644 --- a/src/soc/intel/common/block/include/intelblocks/smihandler.h +++ b/src/soc/intel/common/block/include/intelblocks/smihandler.h @@ -10,41 +10,11 @@ struct global_nvs; /* - * The register value is used with get_reg and set_reg - */ -enum smm_reg { - RAX, - RBX, - RCX, - RDX, -}; - -struct smm_save_state_ops { - /* return io_misc_info from SMM Save State Area */ - uint32_t (*get_io_misc_info)(void *state); - - /* return value of the requested register from - * SMM Save State Area - */ - uint64_t (*get_reg)(void *state, enum smm_reg reg); - - void (*set_reg)(void *state, enum smm_reg reg, uint64_t val); -}; - -typedef void (*smi_handler_t)(const struct smm_save_state_ops *save_state_ops); - -/* - * SOC SMI Handler has to provide this structure which has methods to access - * the SOC specific SMM Save State Area - */ -const struct smm_save_state_ops *get_smm_save_state_ops(void); - -/* * southbridge_smi should be defined inside SOC specific code and should have * handlers for any SMI events that need to be handled. Default handlers * for some SMI events are provided in soc/intel/common/block/smm/smihandler.c */ -extern const smi_handler_t southbridge_smi[32]; +extern const void (*southbridge_smi[32])(void); #define SMI_HANDLER_SCI_EN(__bit) (1 << (__bit)) @@ -53,79 +23,69 @@ * the SMI event on SLP_EN. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_sleep( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_sleep(void); /* * This function should be implemented in SOC specific code to handle * SMI_APM event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_apmc( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_apmc(void); /* * This function should be implemented in SOC specific code to handle * SMI_PM1 event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_pm1( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_pm1(void); /* * This function should be implemented in SOC specific code to handle * SMI_GPE0 event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_gpe0( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_gpe0(void); /* * This function should be implemented in SOC specific code to handle * MC event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_mc( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_mc(void); /* * This function should be implemented in SOC specific code to handle * minitor event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_monitor( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_monitor(void); /* * This function should be implemented in SOC specific code to handle * SMI_TCO event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_tco( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_tco(void); /* * This function should be implemented in SOC specific code to handle * SMI PERIODIC_STS event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_periodic( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_periodic(void); /* * This function should be implemented in SOC specific code to handle * SMI GPIO_STS event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_gpi( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_gpi(void); /* * This function should be implemented in SOC specific code to handle * SMI ESPI_STS event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_espi( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_espi(void); /* SoC overrides. */ @@ -145,8 +105,4 @@ /* Mainboard handler for ESPI EMIs */ void mainboard_smi_espi_handler(void); - -extern const struct smm_save_state_ops em64t100_smm_ops; - -extern const struct smm_save_state_ops em64t101_smm_ops; #endif diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index b629ef2..d1b9093 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -6,8 +6,7 @@ #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t100_save_state.h> -#include <cpu/intel/em64t101_save_state.h> +#include <cpu/x86/save_state.h> #include <delay.h> #include <device/pci_def.h> #include <elog.h> @@ -26,13 +25,6 @@ #include <spi-generic.h> #include <stdint.h> -/* SoC overrides. */ - -__weak const struct smm_save_state_ops *get_smm_save_state_ops(void) -{ - return &em64t101_smm_ops; -} - /* Specific SOC SMI handler during ramstage finalize phase */ __weak void smihandler_soc_at_finalize(void) { @@ -84,38 +76,6 @@ /* Common Functions */ -static void *find_save_state(const struct smm_save_state_ops *save_state_ops, - int cmd) -{ - int node; - void *state = NULL; - uint32_t io_misc_info; - uint8_t reg_al; - - /* Check all nodes looking for the one that issued the IO */ - for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - io_misc_info = save_state_ops->get_io_misc_info(state); - - /* Check for Synchronous IO (bit0==1) */ - if (!(io_misc_info & (1 << 0))) - continue; - /* Make sure it was a write (bit4==0) */ - if (io_misc_info & (1 << 4)) - continue; - /* Check for APMC IO port */ - if (((io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - /* Check AL against the requested command */ - reg_al = save_state_ops->get_reg(state, RAX); - if (reg_al != cmd) - continue; - break; - } - return state; -} - /* Inherited from cpu/x86/smm.h resulting in a different signature */ void southbridge_smi_set_eos(void) { @@ -170,8 +130,7 @@ } -void smihandler_southbridge_sleep( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_sleep(void) { uint32_t reg32; uint8_t slp_typ; @@ -284,11 +243,9 @@ smihandler_soc_at_finalize(); } -void smihandler_southbridge_apmc( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_apmc(void) { uint8_t reg8; - void *state = NULL; static int smm_initialized = 0; /* Emulate B2 register as the FADT / Linux expects it */ @@ -325,12 +282,10 @@ "SMI#: SMM structures already initialized!\n"); return; } - state = find_save_state(save_state_ops, reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - uint32_t reg_ebx = save_state_ops->get_reg(state, RBX); - gnvs = (struct global_nvs *)(uintptr_t)reg_ebx; - smm_initialized = 1; + int node = get_apmc_node(reg8); + if (node >= 0) { + if (!get_save_state_reg(RBX, node, &gnvs, sizeof(gnvs))) + smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; @@ -350,8 +305,7 @@ mainboard_smi_apmc(reg8); } -void smihandler_southbridge_pm1( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_pm1(void) { uint16_t pm1_sts = pmc_clear_pm1_status(); u16 pm1_en = pmc_read_pm1_enable(); @@ -368,14 +322,12 @@ } } -void smihandler_southbridge_gpe0( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_gpe0(void) { pmc_clear_all_gpe_status(); } -void smihandler_southbridge_tco( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_tco(void) { uint32_t tco_sts = pmc_clear_tco_status(); @@ -399,8 +351,7 @@ } } -void smihandler_southbridge_periodic( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_periodic(void) { uint32_t reg32; @@ -412,8 +363,7 @@ printk(BIOS_DEBUG, "Periodic SMI.\n"); } -void smihandler_southbridge_gpi( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_gpi(void) { struct gpi_status smi_sts; @@ -424,8 +374,7 @@ gpi_clear_get_smi_status(&smi_sts); } -void smihandler_southbridge_espi( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_espi(void) { mainboard_smi_espi_handler(); } @@ -444,7 +393,6 @@ { int i; uint32_t smi_sts; - const struct smm_save_state_ops *save_state_ops; /* * We need to clear the SMI status registers, or we won't see what's @@ -463,15 +411,13 @@ if (!smi_sts) return; - save_state_ops = get_smm_save_state_ops(); - /* Call SMI sub handler for each of the status bits */ for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) { if (!(smi_sts & (1 << i))) continue; if (southbridge_smi[i] != NULL) { - southbridge_smi[i](save_state_ops); + southbridge_smi[i](); } else { printk(BIOS_DEBUG, "SMI_STS[%d] occurred, but no " @@ -479,119 +425,3 @@ } } } - -static uint32_t em64t100_smm_save_state_get_io_misc_info(void *state) -{ - em64t100_smm_state_save_area_t *smm_state = state; - return smm_state->io_misc_info; -} - -static uint64_t em64t100_smm_save_state_get_reg(void *state, enum smm_reg reg) -{ - uintptr_t value = 0; - em64t100_smm_state_save_area_t *smm_state = state; - - switch (reg) { - case RAX: - value = smm_state->rax; - break; - case RBX: - value = smm_state->rbx; - break; - case RCX: - value = smm_state->rcx; - break; - case RDX: - value = smm_state->rdx; - break; - default: - break; - } - return value; -} - -static void em64t100_smm_save_state_set_reg(void *state, enum smm_reg reg, - uint64_t val) -{ - em64t100_smm_state_save_area_t *smm_state = state; - switch (reg) { - case RAX: - smm_state->rax = val; - break; - case RBX: - smm_state->rbx = val; - break; - case RCX: - smm_state->rcx = val; - break; - case RDX: - smm_state->rdx = val; - break; - default: - break; - } -} - -static uint32_t em64t101_smm_save_state_get_io_misc_info(void *state) -{ - em64t101_smm_state_save_area_t *smm_state = state; - return smm_state->io_misc_info; -} - -static uint64_t em64t101_smm_save_state_get_reg(void *state, enum smm_reg reg) -{ - uintptr_t value = 0; - em64t101_smm_state_save_area_t *smm_state = state; - - switch (reg) { - case RAX: - value = smm_state->rax; - break; - case RBX: - value = smm_state->rbx; - break; - case RCX: - value = smm_state->rcx; - break; - case RDX: - value = smm_state->rdx; - break; - default: - break; - } - return value; -} - -static void em64t101_smm_save_state_set_reg(void *state, enum smm_reg reg, - uint64_t val) -{ - em64t101_smm_state_save_area_t *smm_state = state; - switch (reg) { - case RAX: - smm_state->rax = val; - break; - case RBX: - smm_state->rbx = val; - break; - case RCX: - smm_state->rcx = val; - break; - case RDX: - smm_state->rdx = val; - break; - default: - break; - } -} - -const struct smm_save_state_ops em64t100_smm_ops = { - .get_io_misc_info = em64t100_smm_save_state_get_io_misc_info, - .get_reg = em64t100_smm_save_state_get_reg, - .set_reg = em64t100_smm_save_state_set_reg, -}; - -const struct smm_save_state_ops em64t101_smm_ops = { - .get_io_misc_info = em64t101_smm_save_state_get_io_misc_info, - .get_reg = em64t101_smm_save_state_get_reg, - .set_reg = em64t101_smm_save_state_set_reg, -}; diff --git a/src/soc/intel/common/block/smm/smitraphandler.c b/src/soc/intel/common/block/smm/smitraphandler.c index 99825f1..6900061 100644 --- a/src/soc/intel/common/block/smm/smitraphandler.c +++ b/src/soc/intel/common/block/smm/smitraphandler.c @@ -40,8 +40,7 @@ return 0; } -void smihandler_southbridge_mc( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_mc(void) { u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN); @@ -52,8 +51,7 @@ printk(BIOS_DEBUG, "Microcontroller SMI.\n"); } -void smihandler_southbridge_monitor( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_monitor(void) { #define IOTRAP(x) (trap_sts & (1 << x)) u32 trap_cycle; diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index 5eecba7..397a6ec 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -7,7 +7,7 @@ #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t100_save_state.h> +#include <cpu/x86/save_state.h> #include <device/pci_def.h> #include <intelblocks/fast_spi.h> #include <spi-generic.h> @@ -146,42 +146,6 @@ } } -/* - * Look for Synchronous IO SMI and use save state from that - * core in case we are not running on the same core that - * initiated the IO transaction. - */ -static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) -{ - em64t100_smm_state_save_area_t *state; - int node; - - /* Check all nodes looking for the one that issued the IO */ - for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0==1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4==0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - - /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) - continue; - - return state; - } - - return NULL; -} - static void finalize(void) { static int finalize_done; @@ -237,14 +201,12 @@ "SMI#: SMM structures already initialized!\n"); return; } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((uint32_t)state->rbx); - smm_initialized = 1; + int node = get_apmc_node(reg8); + if (node >= 0) { + if (!get_save_state_reg(RBX, node, &gnvs, sizeof(gnvs))) + smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } - break; } mainboard_smi_apmc(reg8); diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index fbbbbdb..8ff0e6e 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -25,7 +25,7 @@ heci_disable(); } -const smi_handler_t southbridge_smi[SMI_STS_BITS] = { +const void (*southbridge_smi[SMI_STS_BITS])(void) = { [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, [APM_STS_BIT] = smihandler_southbridge_apmc, [PM1_STS_BIT] = smihandler_southbridge_pm1, diff --git a/src/soc/intel/jasperlake/smihandler.c b/src/soc/intel/jasperlake/smihandler.c index 6d31adf..4246b27 100644 --- a/src/soc/intel/jasperlake/smihandler.c +++ b/src/soc/intel/jasperlake/smihandler.c @@ -25,7 +25,7 @@ heci_disable(); } -const smi_handler_t southbridge_smi[SMI_STS_BITS] = { +const void (*southbridge_smi[SMI_STS_BITS])(void) = { [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, [APM_STS_BIT] = smihandler_southbridge_apmc, [PM1_STS_BIT] = smihandler_southbridge_pm1, diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index 177010c..5df890c 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -3,7 +3,7 @@ #include <intelblocks/smihandler.h> #include <soc/pm.h> -const smi_handler_t southbridge_smi[SMI_STS_BITS] = { +const void (*southbridge_smi[SMI_STS_BITS])(void) = { [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, [APM_STS_BIT] = smihandler_southbridge_apmc, [PM1_STS_BIT] = smihandler_southbridge_pm1, diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c index 40ed25e..a757cca 100644 --- a/src/soc/intel/tigerlake/smihandler.c +++ b/src/soc/intel/tigerlake/smihandler.c @@ -25,7 +25,7 @@ heci_disable(); } -const smi_handler_t southbridge_smi[SMI_STS_BITS] = { +const void (*southbridge_smi[SMI_STS_BITS])(void) [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, [APM_STS_BIT] = smihandler_southbridge_apmc, [PM1_STS_BIT] = smihandler_southbridge_pm1, diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index cb42832..bc4896a 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -269,7 +269,6 @@ return; } int node = get_apmc_node(reg8); - if (node >= 0) { if (!get_save_state_reg(RBX, node, &gnvs, sizeof(gnvs))) smm_initialized = 1; diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 007b383..14f45da 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -7,7 +7,7 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> +#include <cpu/x86/save_state.h> #include <elog.h> #include <halt.h> #include <option.h> @@ -182,42 +182,6 @@ } } -/* - * Look for Synchronous IO SMI and use save state from that - * core in case we are not running on the same core that - * initiated the IO transaction. - */ -static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) -{ - em64t101_smm_state_save_area_t *state; - int node; - - /* Check all nodes looking for the one that issued the IO */ - for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0 == 1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4 == 0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - - /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) - continue; - - return state; - } - - return NULL; -} - static void southbridge_smi_apmc(void) { u8 reg8; -- To view, visit https://review.coreboot.org/c/coreboot/+/45477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08349fd4f8d0a3dcd64f70ddfc9d18abcafb9d3b Gerrit-Change-Number: 45477 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/denverton_ns: Update GNVS using common save state accessors
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45819 ) Change subject: soc/intel/denverton_ns: Update GNVS using common save state accessors ...................................................................... soc/intel/denverton_ns: Update GNVS using common save state accessors Change-Id: I53e8b010b9e057b3a6b856ab9bfd7e0ac13f4593 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/denverton_ns/smihandler.c 1 file changed, 5 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/45819/1 diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index 5eecba7..92fa133 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -7,7 +7,7 @@ #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t100_save_state.h> +#include <cpu/x86/save_state.h> #include <device/pci_def.h> #include <intelblocks/fast_spi.h> #include <spi-generic.h> @@ -146,42 +146,6 @@ } } -/* - * Look for Synchronous IO SMI and use save state from that - * core in case we are not running on the same core that - * initiated the IO transaction. - */ -static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) -{ - em64t100_smm_state_save_area_t *state; - int node; - - /* Check all nodes looking for the one that issued the IO */ - for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0==1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4==0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - - /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) - continue; - - return state; - } - - return NULL; -} - static void finalize(void) { static int finalize_done; @@ -200,7 +164,6 @@ static void southbridge_smi_apmc(void) { uint8_t reg8; - em64t100_smm_state_save_area_t *state; /* Emulate B2 register as the FADT / Linux expects it */ @@ -237,11 +200,10 @@ "SMI#: SMM structures already initialized!\n"); return; } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((uint32_t)state->rbx); - smm_initialized = 1; + int node = get_apmc_node(reg8); + if (node >= 0) { + if (!get_save_state_reg(RBX, node, &gnvs, sizeof(gnvs))) + smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; -- To view, visit https://review.coreboot.org/c/coreboot/+/45819 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53e8b010b9e057b3a6b856ab9bfd7e0ac13f4593 Gerrit-Change-Number: 45819 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/braswell: Update GNVS using common save state accessors
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45763 ) Change subject: soc/intel/braswell: Update GNVS using common save state accessors ...................................................................... soc/intel/braswell: Update GNVS using common save state accessors Change-Id: I5a7ba328968cb5c29a6e7c3e1eda8663c77cd676 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/braswell/smihandler.c 1 file changed, 7 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/45763/1 diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index 4d3b67e..2af6613 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -7,7 +7,7 @@ #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t100_save_state.h> +#include <cpu/x86/save_state.h> #include <device/pci_def.h> #include <elog.h> #include <soc/nvs.h> @@ -184,45 +184,9 @@ } } -/* - * Look for Synchronous IO SMI and use save state from that core in case - * we are not running on the same core that initiated the IO transaction. - */ -static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) -{ - em64t100_smm_state_save_area_t *state; - int node; - - /* Check all nodes looking for the one that issued the IO */ - for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0==1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4==0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - - /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) - continue; - - return state; - } - - return NULL; -} - static void southbridge_smi_apmc(void) { uint8_t reg8; - em64t100_smm_state_save_area_t *state; /* Emulate B2 register as the FADT / Linux expects it */ @@ -257,10 +221,12 @@ printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); return; } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((uint32_t)state->rbx); + int node = get_apmc_node(reg8); + if (node >= 0) { + if (get_save_state_reg(RBX, node, &gnvs, sizeof(gnvs))) { + printk(BIOS_ERR, "SMI#: Unable to get GNVS pointer\n"); + return; + } if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); return; -- To view, visit https://review.coreboot.org/c/coreboot/+/45763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a7ba328968cb5c29a6e7c3e1eda8663c77cd676 Gerrit-Change-Number: 45763 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/baytrail: Update GNVS using common save state accessors
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45762 ) Change subject: soc/intel/baytrail: Update GNVS using common save state accessors ...................................................................... soc/intel/baytrail: Update GNVS using common save state accessors Change-Id: Ifbb9506cad9949f723f8a2eb05a95c426742a06e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/baytrail/smihandler.c 1 file changed, 7 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/45762/1 diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index cf47341..1048a3a 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -6,7 +6,7 @@ #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t100_save_state.h> +#include <cpu/x86/save_state.h> #include <device/pci_def.h> #include <elog.h> #include <halt.h> @@ -152,41 +152,6 @@ } /* - * Look for Synchronous IO SMI and use save state from that core in case - * we are not running on the same core that initiated the IO transaction. - */ -static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) -{ - em64t100_smm_state_save_area_t *state; - int node; - - /* Check all nodes looking for the one that issued the IO */ - for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0==1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4==0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - - /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) - continue; - - return state; - } - - return NULL; -} - -/* * soc_legacy: A payload (Depthcharge) has indicated that the * legacy payload (SeaBIOS) is being loaded. Switch devices that are * in ACPI mode to PCI mode so that non-ACPI drivers may work. @@ -243,7 +208,6 @@ static void southbridge_smi_apmc(void) { uint8_t reg8; - em64t100_smm_state_save_area_t *state; /* Emulate B2 register as the FADT / Linux expects it */ @@ -278,10 +242,12 @@ printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); return; } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((uint32_t)state->rbx); + int node = get_apmc_node(reg8); + if (node >= 0) { + if (get_save_state_reg(RBX, node, &gnvs, sizeof(gnvs))) { + printk(BIOS_ERR, "SMI#: ERROR: unable to get GNVS pointer\n"); + return; + } if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); return; -- To view, visit https://review.coreboot.org/c/coreboot/+/45762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbb9506cad9949f723f8a2eb05a95c426742a06e Gerrit-Change-Number: 45762 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: Update GNVS using common save state accessors
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45761 ) Change subject: soc/intel/broadwell: Update GNVS using common save state accessors ...................................................................... soc/intel/broadwell: Update GNVS using common save state accessors Change-Id: I66970b5d4d6408ed1810146d03a803e1cd54951d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/broadwell/smihandler.c 1 file changed, 7 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/45761/1 diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 8068a3c..ee0a817 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -9,7 +9,7 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> +#include <cpu/x86/save_state.h> #include <spi-generic.h> #include <elog.h> #include <halt.h> @@ -235,46 +235,9 @@ } } -/* - * Look for Synchronous IO SMI and use save state from that - * core in case we are not running on the same core that - * initiated the IO transaction. - */ -static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) -{ - em64t101_smm_state_save_area_t *state; - int node; - - /* Check all nodes looking for the one that issued the IO */ - for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0==1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4==0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - - /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) - continue; - - return state; - } - - return NULL; -} - static void southbridge_smi_apmc(void) { u8 reg8; - em64t101_smm_state_save_area_t *state; /* Emulate B2 register as the FADT / Linux expects it */ @@ -300,10 +263,12 @@ "SMI#: SMM structures already initialized!\n"); return; } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); + int node = get_apmc_node(reg8); + if (node >= 0) { + if (get_save_state_reg(RBX, node, &gnvs, sizeof(gnvs))) { + printk(BIOS_ERR, "SMI#: ERROR: unable to get GNVS pointer\n"); + return; + } if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); return; -- To view, visit https://review.coreboot.org/c/coreboot/+/45761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66970b5d4d6408ed1810146d03a803e1cd54951d Gerrit-Change-Number: 45761 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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