Change in coreboot[master]: soc/intel/common: Move reset request into intel_fw_update

[Sridhar Siricilla (Code Review)]

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46819 )

Change subject: soc/intel/common: Move reset request into intel_fw_update
......................................................................

soc/intel/common: Move reset request into intel_fw_update

The patch implements below functionalities:
 1. Move reset request from CSE FW Update
 2. Implement intel_fw_sync(), which triggers UCODE and CSE Lite FW update and
    trigger global reset if one of the FW update requests reset.

This patch prevents triggering global reset having separate reset request in
UCODE update or CSE Lite FW Update.

Signed-off-by: Sridhar Siricilla 
Change-Id: I50da4206de05e552de68af7fa0afaef2dac33004
---
A src/soc/intel/common/basecode/fw_update/fw_update.c
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
3 files changed, 105 insertions(+), 52 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/46819/1

diff --git a/src/soc/intel/common/basecode/fw_update/fw_update.c b/src/soc/intel/common/basecode/fw_update/fw_update.c
new file mode 100644
index 0000000..45d2d968
--- /dev/null
+++ b/src/soc/intel/common/basecode/fw_update/fw_update.c
@@ -0,0 +1,63 @@
+#include <bootstate.h>
+#include <console/console.h>
+#include <halt.h>
+#include <intelbasecode/ucode_update.h>
+#include <reset.h>
+#include <security/vboot/misc.h>
+#include <security/vboot/vboot_common.h>
+#include <soc/intel/common/reset.h>
+#include <vb2_api.h>
+#include <intelblocks/cse.h>
+
+__weak void cse_board_reset(void)
+{
+        /* Default weak implementation, does nothing. */
+}
+
+void trigger_global_reset() {
+
+        cse_board_reset();
+
+        /* If board does not perform the reset, then perform global_reset */
+        do_global_reset();
+
+        die("cse_lite: Failed to reset the system\n");
+}
+
+static uint8_t update_ucode(void)
+{
+	if (CONFIG(INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE)) {
+		uint8_t reset_req = 0;
+		if (update_ucode_and_topswap_state(&reset_req)) {
+			/* Update failed */
+			if (CONFIG(VBOOT)) {
+				printk(BIOS_DEBUG, "ucode: Failed to update microcode\n");
+				struct vb2_context *ctx = vboot_get_context();
+				if (ctx == NULL)
+					die("ucode: Failed to trigger recovery mode\n");
+				vb2api_fail(ctx, 0x36, 0x0);
+				vboot_save_data(ctx);
+				vboot_reboot();
+			}
+		}
+		return reset_req;
+	}
+}
+
+static void intel_fw_update(void *unused)
+{
+	if (update_ucode() || cse_fw_sync())
+		trigger_global_reset();
+}
+
+
+#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_JASPERLAKE)
+
+/*
+ * This needs to happen after the MRC cache write to avoid a 2nd
+ * memory training sequence.
+ */
+BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, intel_fw_update, NULL);
+#else
+BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, intel_fw_update, NULL);
+#endif
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index 77a8d5f..6006e13 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -414,43 +414,28 @@
    return true;
 }

-__weak void cse_board_reset(void)
-{
-	/* Default weak implementation, does nothing. */
-}
-
-/* Set the CSE's next boot partition and issues system reset */
-static bool cse_set_and_boot_from_next_bp(enum boot_partition_id bp)
-{
-	if (!cse_set_next_boot_partition(bp))
-		return false;
-
-	/* Allow the board to perform a reset for CSE RO<->RW jump */
-	cse_board_reset();
-
-	/* If board does not perform the reset, then perform global_reset */
-	do_global_reset();
-
-	die("cse_lite: Failed to reset the system\n");
-
-	/* Control never reaches here */
-	return false;
-}
-
-static bool cse_boot_to_rw(const struct cse_bp_info *cse_bp_info)
+static bool cse_set_next_bp_to_rw(const struct cse_bp_info *cse_bp_info, uint8_t *reset_req)
 {
    if (cse_get_current_bp(cse_bp_info) == RW)
    	return true;

-	return cse_set_and_boot_from_next_bp(RW);
+	if (!cse_set_next_boot_partition(RW))
+		return false;
+
+	*reset_req = 1;
+	return true;
 }

-static bool cse_boot_to_ro(const struct cse_bp_info *cse_bp_info)
+static bool cse_set_next_bp_to_ro(const struct cse_bp_info *cse_bp_info, uint8_t *reset_req)
 {
    if (cse_get_current_bp(cse_bp_info) == RO)
    	return true;

-	return cse_set_and_boot_from_next_bp(RO);
+	if (!cse_set_next_boot_partition(RO))
+		return false;
+
+	*reset_req = 1;
+	return truel
 }

static bool cse_get_rw_rdev(struct region_device *rdev)
@@ -701,7 +686,7 @@
  * It returns true if RW partition doesn't indicate BP_STATUS_DATA_FAILURE
  * otherwise false if any operation fails.
  */
-static bool cse_fix_data_failure_err(const struct cse_bp_info *cse_bp_info)
+static bool cse_fix_data_failure_err(const struct cse_bp_info *cse_bp_info, uint8_t *reset_req)
 {
    /*
     * If RW partition status indicates BP_STATUS_DATA_FAILURE,
@@ -715,7 +700,7 @@
    if (!cse_data_clear_request(cse_bp_info))
    	return false;

-	return cse_boot_to_rw(cse_bp_info);
+	return cse_set_next_bp_to_rw(cse_bp_info, reset_req);
 }

static bool cse_erase_rw_region(const struct region_device *target_rdev)
@@ -798,16 +783,19 @@
 }

static bool cse_prep_for_rw_update(const struct cse_bp_info *cse_bp_info,
-		const struct cse_cbfs_rw_info *source_info)
+		const struct cse_cbfs_rw_info *source_info, uint8_t *reset_req)
 {
    /*
     * To set CSE's operation mode to HMRFPO mode:
     * 1. Ensure CSE to boot from RO(BP1)
     * 2. Send HMRFPO_ENABLE command to CSE
     */
-	if (!cse_boot_to_ro(cse_bp_info))
+	if (!cse_set_boot_to_ro(cse_bp_info, reset_req))
    	return false;

+	if (*reset_req)
+		return true;
+
    if (cse_is_downgrade_instance(cse_bp_info, source_info) &&
    		!cse_data_clear_request(cse_bp_info)) {
    	printk(BIOS_ERR, "cse_lite: CSE FW downgrade is aborted\n");
@@ -818,7 +806,8 @@
 }

static enum csme_failure_reason cse_trigger_fw_update(const struct cse_bp_info *cse_bp_info,
-		const struct cse_cbfs_rw_info *source_info, struct region_device *target_rdev)
+		const struct cse_cbfs_rw_info *source_info, struct region_device *target_rdev,
+		uint8_t *reset_req)
 {
    struct region_device source_rdev;

@@ -836,7 +825,7 @@
    	}
    }

-	if (!cse_prep_for_rw_update(cse_bp_info, source_info)) {
+	if (!cse_prep_for_rw_update(cse_bp_info, source_info, reset_req)) {
    	rv = CSE_LITE_SKU_COMMUNICATION_ERROR;
    	goto error_exit;
    }
@@ -850,7 +839,7 @@
 }

static uint8_t cse_fw_update(const struct cse_bp_info *cse_bp_info,
-		const struct region_device *source_info_rdev)
+		const struct region_device *source_info_rdev, uint8_t *reset_req)
 {
    struct region_device target_rdev;

@@ -869,7 +858,7 @@

if (cse_is_update_required(cse_bp_info, &source_info, &target_rdev)) {
    	printk(BIOS_DEBUG, "cse_lite: CSE RW update is initiated\n");
-		return cse_trigger_fw_update(cse_bp_info, &source_info, &target_rdev);
+		return cse_trigger_fw_update(cse_bp_info, &source_info, &target_rdev, reset_req);
    }

if (!cse_is_rw_bp_status_valid(cse_bp_info))
@@ -878,19 +867,19 @@
    return 0;
 }

-void cse_fw_sync(void *unused)
+uint8_t cse_fw_sync(void)
 {
    static struct get_bp_info_rsp cse_bp_info;

if (vboot_recovery_mode_enabled()) {
    	printk(BIOS_DEBUG, "cse_lite: Skip switching to RW in the recovery path\n");
-		return;
+		return 0;
    }

/* If CSE SKU type is not Lite, skip enabling CSE Lite SKU */
    if (!cse_is_hfs3_fw_sku_lite()) {
    	printk(BIOS_ERR, "cse_lite: Not a CSE Lite SKU\n");
-		return;
+		return 0;
    }

if (!cse_get_bp_info(&cse_bp_info)) {
@@ -898,9 +887,15 @@
    	cse_trigger_recovery(CSE_LITE_SKU_COMMUNICATION_ERROR);
    }

-	if (!cse_fix_data_failure_err(&cse_bp_info.bp_info))
+	uint8_t reset_req = 0;
+
+	if (!cse_fix_data_failure_err(&cse_bp_info.bp_info, &reset_req))
    	cse_trigger_recovery(CSE_LITE_SKU_DATA_WIPE_ERROR);

+	if(reset_req)
+		return reset_req;
+
+
    /*
     * If CSE CBFS RW blob metadata is present in CBFS, then trigger CSE firmware update.
     * The driver triggers recovery if CSE CBFS RW metadata is present in the CBFS and CSE
@@ -909,23 +904,17 @@
    uint8_t rv;
    struct region_device source_info_rdev;
    if (cse_get_cbfs_rdev(&source_info_rdev)) {
-		rv = cse_fw_update(&cse_bp_info.bp_info, &source_info_rdev);
+		rv = cse_fw_update(&cse_bp_info.bp_info, &source_info_rdev, &reset_req);
    	if (rv)
    		cse_trigger_recovery(rv);
    }

-	if (!cse_boot_to_rw(&cse_bp_info.bp_info)) {
+	if(reset_req)
+		return reset_req;
+
+	if (!cse_set_next_bp_to_rw(&cse_bp_info.bp_info, &reset_req)) {
    	printk(BIOS_ERR, "cse_lite: Failed to switch to RW\n");
    	cse_trigger_recovery(CSE_LITE_SKU_RW_SWITCH_ERROR);
    }
+	return reset_req;
 }
-
-#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_JASPERLAKE)
-/*
- * This needs to happen after the MRC cache write to avoid a 2nd
- * memory training sequence.
- */
-BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, cse_fw_sync, NULL);
-#else
-BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, cse_fw_sync, NULL);
-#endif
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index f554933..0ac5d74 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -216,8 +216,9 @@
  * boot from RW and triggers recovery mode if CSE fails to jump to RW.
  * In software triggered recovery mode, the function allows CSE to boot from whatever is
  * currently selected partition.
+ * Returns 1 if reset is required otherwise 0.
  */
-void cse_fw_sync(void *unused);
+uint8_t cse_fw_sync(void);

/* Perform a board-specific reset sequence for CSE RO<->RW jump */
 void cse_board_reset(void);

[Sridhar Siricilla (Code Review)]

Sridhar Siricilla has removed Patrick Rudolph from this change.  ( https://review.coreboot.org/c/coreboot/+/46819 )

Change subject: soc/intel/common: Move reset request into intel_fw_update
......................................................................

Removed reviewer Patrick Rudolph.

[Sridhar Siricilla (Code Review)]

Hello Patrick Georgi, Martin Roth, Jamie Ryu, Rizwan Qureshi, Sugnan Prabhu S, Krishna P Bhat D, Raj Astekar, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46819

to look at the new patch set (#6).

Change subject: soc/intel/common: Move reset request into intel_fw_update
......................................................................

soc/intel/common: Move reset request into intel_fw_update

The patch implements below functionalities:
 1. Move reset request from CSE FW Update & UCODE Update.
 2. Implement intel_fw_sync(), which triggers UCODE and CSE Lite FW update.
 3. intel_fw_sync() triggers global reset if either of CSE Lite FW Update
    or UCODE Update requests reset.

Signed-off-by: Sridhar Siricilla 
Signed-off-by: Jamie Ryu 
Change-Id: I50da4206de05e552de68af7fa0afaef2dac33004
---
M src/soc/intel/common/basecode/fw_update/Makefile.inc
A src/soc/intel/common/basecode/fw_update/fw_update.c
M src/soc/intel/common/basecode/fw_update/ucode_update.c
A src/soc/intel/common/basecode/include/intelbasecode/fw_update.h
M src/soc/intel/common/basecode/include/intelbasecode/ucode_update.h
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
7 files changed, 122 insertions(+), 79 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/46819/6

[Sugnan Prabhu S (Code Review)]

Attention is currently required from: Sugnan Prabhu S.
Sugnan Prabhu S has uploaded a new patch set (#7) to the change originally created by Sridhar Siricilla. ( https://review.coreboot.org/c/coreboot/+/46819 )

Change subject: soc/intel/common: Move reset request into intel_fw_update
......................................................................

soc/intel/common: Move reset request into intel_fw_update

The patch implements below functionalities:
 1. Move reset request from CSE FW Update & UCODE Update.
 2. Implement intel_fw_sync(), which triggers UCODE and CSE Lite FW update.
 3. intel_fw_sync() triggers global reset if either of CSE Lite FW Update
    or UCODE Update requests reset.

Signed-off-by: Sridhar Siricilla 
Signed-off-by: Jamie Ryu 
Change-Id: I50da4206de05e552de68af7fa0afaef2dac33004
---
M src/soc/intel/common/basecode/fw_update/Makefile.inc
A src/soc/intel/common/basecode/fw_update/fw_update.c
M src/soc/intel/common/basecode/fw_update/ucode_update.c
A src/soc/intel/common/basecode/include/intelbasecode/fw_update.h
A src/soc/intel/common/basecode/include/intelbasecode/ucode_update.h
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
7 files changed, 135 insertions(+), 64 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/46819/7

[Jamie Ryu (Code Review)]

Attention is currently required from: Sugnan Prabhu S, Sridhar Siricilla.
Jamie Ryu has uploaded a new patch set (#8) to the change originally created by Sridhar Siricilla. ( https://review.coreboot.org/c/coreboot/+/46819 )

Change subject: soc/intel/common: Move reset request into intel_fw_update
......................................................................

soc/intel/common: Move reset request into intel_fw_update

The patch implements below functionalities:
 1. Move reset request from CSE FW Update & UCODE Update.
 2. Implement intel_fw_sync(), which triggers UCODE and CSE Lite FW update.
 3. intel_fw_sync() triggers global reset if either of CSE Lite FW Update
    or UCODE Update requests reset.

Signed-off-by: Sridhar Siricilla 
Signed-off-by: Jamie Ryu 
Change-Id: I50da4206de05e552de68af7fa0afaef2dac33004
---
M src/soc/intel/alderlake/romstage/romstage.c
M src/soc/intel/common/basecode/fw_update/Makefile.inc
A src/soc/intel/common/basecode/fw_update/fw_update.c
M src/soc/intel/common/basecode/fw_update/ucode_update.c
A src/soc/intel/common/basecode/include/intelbasecode/fw_update.h
M src/soc/intel/common/basecode/include/intelbasecode/ucode_update.h
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
M src/soc/intel/jasperlake/romstage/romstage.c
M src/soc/intel/tigerlake/romstage/romstage.c
10 files changed, 149 insertions(+), 85 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/46819/8

[build bot (Jenkins) (Code Review)]

Attention is currently required from: Jamie Ryu, Sugnan Prabhu S.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46819 )

Change subject: soc/intel/common: Move reset request into intel_fw_update
......................................................................

Patch Set 8:

(6 comments)

File src/soc/intel/alderlake/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/46819/comment/bc330ca9_25e1b383 
PS8, Line 139: 		if (CONFIG(SOC_INTEL_CSE_LITE_SKU) || CONFIG(INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE))
line over 96 characters

File src/soc/intel/common/basecode/fw_update/ucode_update.c:

https://review.coreboot.org/c/coreboot/+/46819/comment/860a9123_a447f98e 
PS8, Line 252:                	printk(BIOS_INFO, "ucode: recovery mode enabled\n");
code indent should use tabs where possible

https://review.coreboot.org/c/coreboot/+/46819/comment/3061f5a8_e5fcc9b2 
PS8, Line 252:                	printk(BIOS_INFO, "ucode: recovery mode enabled\n");
please, no space before tabs

https://review.coreboot.org/c/coreboot/+/46819/comment/ad26dbc2_f33a2767 
PS8, Line 252:                	printk(BIOS_INFO, "ucode: recovery mode enabled\n");
please, no spaces at the start of a line

File src/soc/intel/jasperlake/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/46819/comment/2492e261_932ba4b3 
PS8, Line 147: 		if (CONFIG(SOC_INTEL_CSE_LITE_SKU) || CONFIG(INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE))
line over 96 characters

File src/soc/intel/tigerlake/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/46819/comment/a5f102c9_d9613569 
PS8, Line 146: 		if (CONFIG(SOC_INTEL_CSE_LITE_SKU) || CONFIG(INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE))
line over 96 characters

[Jamie Ryu (Code Review)]

Attention is currently required from: Jamie Ryu, Sugnan Prabhu S, Sridhar Siricilla.
Jamie Ryu has uploaded a new patch set (#9) to the change originally created by Sridhar Siricilla. ( https://review.coreboot.org/c/coreboot/+/46819 )

Change subject: soc/intel/common: Move reset request into intel_fw_update
......................................................................

soc/intel/common: Move reset request into intel_fw_update

The patch implements below functionalities:
 1. Move reset request from CSE FW Update & UCODE Update.
 2. Implement intel_fw_sync(), which triggers UCODE and CSE Lite FW update.
 3. intel_fw_sync() triggers global reset if either of CSE Lite FW Update
    or UCODE Update requests reset.

Signed-off-by: Sridhar Siricilla 
Signed-off-by: Jamie Ryu 
Change-Id: I50da4206de05e552de68af7fa0afaef2dac33004
---
M src/soc/intel/alderlake/romstage/romstage.c
M src/soc/intel/common/basecode/fw_update/Makefile.inc
A src/soc/intel/common/basecode/fw_update/fw_update.c
M src/soc/intel/common/basecode/fw_update/ucode_update.c
A src/soc/intel/common/basecode/include/intelbasecode/fw_update.h
M src/soc/intel/common/basecode/include/intelbasecode/ucode_update.h
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
M src/soc/intel/jasperlake/romstage/romstage.c
M src/soc/intel/tigerlake/romstage/romstage.c
10 files changed, 151 insertions(+), 84 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/46819/9

[Jamie Ryu (Code Review)]

Attention is currently required from: Jamie Ryu, Sugnan Prabhu S.
Jamie Ryu has uploaded a new patch set (#10) to the change originally created by Sridhar Siricilla. ( https://review.coreboot.org/c/coreboot/+/46819 )

Change subject: soc/intel/common: Move reset request into intel_fw_update
......................................................................

soc/intel/common: Move reset request into intel_fw_update

The patch implements below functionalities:
 1. Move reset request from CSE FW Update & UCODE Update.
 2. Implement intel_fw_sync(), which triggers UCODE and CSE Lite FW update.
 3. intel_fw_sync() triggers global reset if either of CSE Lite FW Update
    or UCODE Update requests reset.

Signed-off-by: Sridhar Siricilla 
Signed-off-by: Jamie Ryu 
Change-Id: I50da4206de05e552de68af7fa0afaef2dac33004
---
M src/soc/intel/alderlake/romstage/romstage.c
M src/soc/intel/common/basecode/fw_update/Makefile.inc
A src/soc/intel/common/basecode/fw_update/fw_update.c
M src/soc/intel/common/basecode/fw_update/ucode_update.c
A src/soc/intel/common/basecode/include/intelbasecode/fw_update.h
M src/soc/intel/common/basecode/include/intelbasecode/ucode_update.h
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
M src/soc/intel/jasperlake/romstage/romstage.c
M src/soc/intel/tigerlake/romstage/romstage.c
10 files changed, 153 insertions(+), 84 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/46819/10

[Jamie Ryu (Code Review)]

Attention is currently required from: Jamie Ryu, Sugnan Prabhu S.
Jamie Ryu has uploaded a new patch set (#11) to the change originally created by Sridhar Siricilla. ( https://review.coreboot.org/c/coreboot/+/46819 )

Change subject: soc/intel/common: Move reset request into intel_fw_update
......................................................................

soc/intel/common: Move reset request into intel_fw_update

The patch implements below functionalities:
 1. Move reset request from CSE FW Update & UCODE Update.
 2. Implement intel_fw_sync(), which triggers UCODE and CSE Lite FW update.
 3. intel_fw_sync() triggers global reset if either of CSE Lite FW Update
    or UCODE Update requests reset.

Signed-off-by: Sridhar Siricilla 
Signed-off-by: Jamie Ryu 
Change-Id: I50da4206de05e552de68af7fa0afaef2dac33004
---
M src/soc/intel/alderlake/romstage/romstage.c
M src/soc/intel/common/basecode/fw_update/Makefile.inc
A src/soc/intel/common/basecode/fw_update/fw_update.c
M src/soc/intel/common/basecode/fw_update/ucode_update.c
A src/soc/intel/common/basecode/include/intelbasecode/fw_update.h
M src/soc/intel/common/basecode/include/intelbasecode/ucode_update.h
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
M src/soc/intel/jasperlake/romstage/romstage.c
M src/soc/intel/tigerlake/romstage/romstage.c
10 files changed, 152 insertions(+), 84 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/46819/11

[Meera Ravindranath (Code Review)]

Attention is currently required from: Jamie Ryu, Sugnan Prabhu S, Sridhar Siricilla.
Meera Ravindranath has uploaded a new patch set (#12) to the change originally created by Sridhar Siricilla. ( https://review.coreboot.org/c/coreboot/+/46819 )

Change subject: soc/intel/common: Move reset request into intel_fw_update
......................................................................

soc/intel/common: Move reset request into intel_fw_update

The patch implements below functionalities:
 1. Move reset request from CSE FW Update & UCODE Update.
 2. Implement intel_fw_sync(), which triggers UCODE and CSE Lite FW update.
 3. intel_fw_sync() triggers global reset if either of CSE Lite FW Update
    or UCODE Update requests reset.

Signed-off-by: Sridhar Siricilla 
Signed-off-by: Jamie Ryu 
Change-Id: I50da4206de05e552de68af7fa0afaef2dac33004
---
M src/soc/intel/alderlake/romstage/romstage.c
M src/soc/intel/common/basecode/fw_update/Makefile.inc
A src/soc/intel/common/basecode/fw_update/fw_update.c
M src/soc/intel/common/basecode/fw_update/ucode_update.c
A src/soc/intel/common/basecode/include/intelbasecode/fw_update.h
M src/soc/intel/common/basecode/include/intelbasecode/ucode_update.h
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
M src/soc/intel/jasperlake/romstage/romstage.c
M src/soc/intel/tigerlake/romstage/romstage.c
10 files changed, 152 insertions(+), 85 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/46819/12

[Meera Ravindranath (Code Review)]

Attention is currently required from: Jamie Ryu, Tim Wawrzynczak, Sugnan Prabhu S, Sridhar Siricilla, Meera Ravindranath.
Meera Ravindranath has uploaded a new patch set (#13) to the change originally created by Sridhar Siricilla. ( https://review.coreboot.org/c/coreboot/+/46819 )

Change subject: soc/intel/common: Move reset request into intel_fw_update
......................................................................

soc/intel/common: Move reset request into intel_fw_update

The patch implements below functionalities:
 1. Move reset request from CSE FW Update & UCODE Update.
 2. Implement intel_fw_sync(), which triggers UCODE and CSE Lite FW update.
 3. intel_fw_sync() triggers global reset if either of CSE Lite FW Update
    or UCODE Update requests reset.

Signed-off-by: Sridhar Siricilla 
Signed-off-by: Jamie Ryu 
Change-Id: I50da4206de05e552de68af7fa0afaef2dac33004
---
M src/soc/intel/alderlake/romstage/romstage.c
M src/soc/intel/common/basecode/fw_update/Makefile.inc
A src/soc/intel/common/basecode/fw_update/fw_update.c
M src/soc/intel/common/basecode/fw_update/ucode_update.c
A src/soc/intel/common/basecode/include/intelbasecode/fw_update.h
M src/soc/intel/common/basecode/include/intelbasecode/ucode_update.h
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
M src/soc/intel/jasperlake/romstage/romstage.c
M src/soc/intel/tigerlake/romstage/romstage.c
10 files changed, 154 insertions(+), 85 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/46819/13

[Meera Ravindranath (Code Review)]

Attention is currently required from: Jamie Ryu, Tim Wawrzynczak, Sugnan Prabhu S, Sridhar Siricilla, Meera Ravindranath.
Meera Ravindranath has uploaded a new patch set (#14) to the change originally created by Sridhar Siricilla. ( https://review.coreboot.org/c/coreboot/+/46819 )

Change subject: soc/intel/common: Move reset request into intel_fw_update
......................................................................

soc/intel/common: Move reset request into intel_fw_update

The patch implements below functionalities:
 1. Move reset request from CSE FW Update & UCODE Update.
 2. Implement intel_fw_sync(), which triggers UCODE and CSE Lite FW update.
 3. intel_fw_sync() triggers global reset if either of CSE Lite FW Update
    or UCODE Update requests reset.

Signed-off-by: Sridhar Siricilla 
Signed-off-by: Jamie Ryu 
Change-Id: I50da4206de05e552de68af7fa0afaef2dac33004
---
M src/soc/intel/alderlake/romstage/romstage.c
M src/soc/intel/common/basecode/fw_update/Makefile.inc
A src/soc/intel/common/basecode/fw_update/fw_update.c
M src/soc/intel/common/basecode/fw_update/ucode_update.c
A src/soc/intel/common/basecode/include/intelbasecode/fw_update.h
M src/soc/intel/common/basecode/include/intelbasecode/ucode_update.h
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
M src/soc/intel/jasperlake/romstage/romstage.c
M src/soc/intel/tigerlake/romstage/romstage.c
10 files changed, 153 insertions(+), 85 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/46819/14

[Meera Ravindranath (Code Review)]

Attention is currently required from: Jamie Ryu, Tim Wawrzynczak, Sugnan Prabhu S, Meera Ravindranath.
Meera Ravindranath has uploaded a new patch set (#15) to the change originally created by Sridhar Siricilla. ( https://review.coreboot.org/c/coreboot/+/46819 )

Change subject: soc/intel/common: Move reset request into intel_fw_update
......................................................................

soc/intel/common: Move reset request into intel_fw_update

The patch implements below functionalities:
 1. Move reset request from CSE FW Update & UCODE Update.
 2. Implement intel_fw_sync(), which triggers UCODE and CSE Lite FW update.
 3. intel_fw_sync() triggers global reset if either of CSE Lite FW Update
    or UCODE Update requests reset.

Signed-off-by: Sridhar Siricilla 
Signed-off-by: Jamie Ryu 
Change-Id: I50da4206de05e552de68af7fa0afaef2dac33004
---
M src/soc/intel/alderlake/romstage/romstage.c
M src/soc/intel/common/basecode/fw_update/Makefile.inc
A src/soc/intel/common/basecode/fw_update/fw_update.c
M src/soc/intel/common/basecode/fw_update/ucode_update.c
A src/soc/intel/common/basecode/include/intelbasecode/fw_update.h
M src/soc/intel/common/basecode/include/intelbasecode/ucode_update.h
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
M src/soc/intel/jasperlake/romstage/romstage.c
M src/soc/intel/tigerlake/romstage/romstage.c
10 files changed, 155 insertions(+), 86 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/46819/15

[build bot (Jenkins) (Code Review)]

Attention is currently required from: Jamie Ryu, Tim Wawrzynczak, Sugnan Prabhu S, Meera Ravindranath.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46819 )

Change subject: soc/intel/common: Move reset request into intel_fw_update
......................................................................

Patch Set 15:

(1 comment)

File src/soc/intel/common/block/cse/cse_lite.c:

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124285):
https://review.coreboot.org/c/coreboot/+/46819/comment/3b5c86ee_9eac76ca 
PS15, Line 743: 	if (!cse_boot_to_rw(&cse_bp_info.bp_info)) {
suspect code indent for conditional statements (8, 8)

[M] Change in coreboot[master]: soc/intel/common: Move reset request into intel_fw_update

[Martin L Roth (Code Review)]

Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/46819?usp=email )

Change subject: soc/intel/common: Move reset request into intel_fw_update
......................................................................

Abandoned

This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.