coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

1 participants
6700 discussions

Change in coreboot[master]: include/devices/pci_ids.h: Rework indentations
by build bot (Jenkins) (Code Review) 07 Mar '22

07 Mar '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61531 ) Change subject: include/devices/pci_ids.h: Rework indentations ...................................................................... Patch Set 5: (1 comment) File src/include/device/pci_ids.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143251): https://review.coreboot.org/c/coreboot/+/61531/comment/4370c1c8_af0d7fbb PS5, Line 832: #define PCI_DID_PCTECH_SAMURAI_IDE 0x3020 please, no space before tabs -- To view, visit https://review.coreboot.org/c/coreboot/+/61531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I070d5fbeece570aa410637d3b5b2d24137c9401f Gerrit-Change-Number: 61531 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 03:31:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: include/devices/pci_ids.h: Rework indentations
by Felix Singer (Code Review) 07 Mar '22

07 Mar '22

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61531 ) Change subject: include/devices/pci_ids.h: Rework indentations ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/61531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I070d5fbeece570aa410637d3b5b2d24137c9401f Gerrit-Change-Number: 61531 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 03:31:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya/var/kinox: Modify 15W SOC PL2/PL4 default setting
by Dtrain Hsu (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62627 to look at the new patch set (#2). Change subject: mb/google/brya/var/kinox: Modify 15W SOC PL2/PL4 default setting ...................................................................... mb/google/brya/var/kinox: Modify 15W SOC PL2/PL4 default setting Modify 15W SOC PL2/PL4 default setting to 39W/100W for Kinox. BUG=b:213417026 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I2956705f7d26929c7cf2dd4e852fc61b619a83e5 --- M src/mainboard/google/brya/variants/kinox/Makefile.inc A src/mainboard/google/brya/variants/kinox/ramstage.c 2 files changed, 69 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/62627/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2956705f7d26929c7cf2dd4e852fc61b619a83e5 Gerrit-Change-Number: 62627 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/brya/var/kinox: Modify 15W SOC PL2/PL4 default value
by Dtrain Hsu (Code Review) 07 Mar '22

07 Mar '22

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62627 ) Change subject: mb/google/brya/var/kinox: Modify 15W SOC PL2/PL4 default value ...................................................................... mb/google/brya/var/kinox: Modify 15W SOC PL2/PL4 default value Modify 15W SOC PL2/PL4 default value to 39W/100W for Kinox. BUG=b:213417026 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I2956705f7d26929c7cf2dd4e852fc61b619a83e5 --- M src/mainboard/google/brya/variants/kinox/Makefile.inc A src/mainboard/google/brya/variants/kinox/ramstage.c 2 files changed, 69 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/62627/1 diff --git a/src/mainboard/google/brya/variants/kinox/Makefile.inc b/src/mainboard/google/brya/variants/kinox/Makefile.inc index 58c4d79..681c764 100644 --- a/src/mainboard/google/brya/variants/kinox/Makefile.inc +++ b/src/mainboard/google/brya/variants/kinox/Makefile.inc @@ -2,3 +2,4 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/kinox/ramstage.c b/src/mainboard/google/brya/variants/kinox/ramstage.c new file mode 100644 index 0000000..9260a8c --- /dev/null +++ b/src/mainboard/google/brya/variants/kinox/ramstage.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <device/device.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <ec/google/chromeec/ec.h> +#include <intelblocks/power_limit.h> + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + { PCI_DEVICE_ID_INTEL_ADL_P_ID_10, 15, 15000, 15000, 39000, 39000, 100000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 15000, 15000, 39000, 39000, 100000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 15000, 15000, 39000, 39000, 100000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 28000, 28000, 64000, 64000, 90000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 28000, 28000, 64000, 64000, 140000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 45, 45000, 45000, 95000, 95000, 125000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_4, 45, 45000, 45000, 115000, 115000, 215000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 45000, 45000, 115000, 115000, 215000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 45000, 45000, 95000, 95000, 125000 }, +}; + +const struct system_power_limits sys_limits[] = { + /* SKU_ID, TDP (Watts), psys_pl2 (Watts) */ + { PCI_DEVICE_ID_INTEL_ADL_P_ID_10, 15, 135 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 135 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 135 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 230 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 230 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 45, 230 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_4, 45, 230 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 230 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 230 }, +}; + +/* + * Psys_pmax considerations. + * + * Given the hardware design in brask, the serial shunt resistor is 0.005ohm. + * The full scale of hardware PSYS signal 1.6v maps to system current 13.52A + * instead of real system power. The equation is shown below: + * PSYS = 1.6v = (0.005ohm x 13.52A) x 50 (INA213, gain 50V/V) x R501/(R501 + R510) + * R501/(R501 + R510) = 0.47 = 15K / (15K + 16.9K) + * + * The Psys_pmax is a SW setting which tells IMVP9.1 the mapping b/w system input + * current and the actual system power. Since there is no voltage information + * from PSYS, different voltage input would map to different Psys_pmax settings: + * For Type-C 15V, the Psys_pmax should be 15v x 13.52A = 202.8W + * For Type-C 20V, the Psys_pmax should be 20v x 13.52A = 270.4W + * For a barrel jack, the Psys_pmax should be 19.5v x 13.52A = 263.6W + * + * Imagine that there is a type-c 100W (20V/5A) connected to DUT w/ full loading, + * and the Psys_pmax setting is 270.4W. Then IMVP9.1 can calculate the current system + * power = 270.4W * 5A / 13.52A = 100W, which is the actual system power. + */ +const struct psys_config psys_config = { + .efficiency = 97, + .psys_imax_ma = 13520, + .bj_volts_mv = 19500 +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config); + variant_update_power_limits(limits, total_entries); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/62627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2956705f7d26929c7cf2dd4e852fc61b619a83e5 Gerrit-Change-Number: 62627 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in blobs[master]: soc/mediatek/mt8195: Update dram.elf from 1.8.1 to 1.9.1
by Rex-BC Chen (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Hello Hung-Te Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/blobs/+/62583 to look at the new patch set (#2). Change subject: soc/mediatek/mt8195: Update dram.elf from 1.8.1 to 1.9.1 ...................................................................... soc/mediatek/mt8195: Update dram.elf from 1.8.1 to 1.9.1 Refactor dramc_param to share more structures (CB:61293). BUG=b:218577927 TEST=dram calibration pass Cq-Depend: chromium:3504704 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I05aac544fa3749c6d43dec2df034e1ebe265ebeb --- M soc/mediatek/mt8195/dram.elf M soc/mediatek/mt8195/dram.elf.md5 M soc/mediatek/mt8195/dram_release_notes.txt 3 files changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/83/62583/2 -- To view, visit https://review.coreboot.org/c/blobs/+/62583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: master Gerrit-Change-Id: I05aac544fa3749c6d43dec2df034e1ebe265ebeb Gerrit-Change-Number: 62583 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/skyrim: Add FW_CONFIG Definition
by Jon Murphy (Code Review) 07 Mar '22

07 Mar '22

Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62626 ) Change subject: mb/google/skyrim: Add FW_CONFIG Definition ...................................................................... mb/google/skyrim: Add FW_CONFIG Definition BUG=b:214415048 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: Ia6bb3f717b3d30fe5f166dfc958024e931a070c8 --- M src/mainboard/google/skyrim/variants/skyrim/overridetree.cb 1 file changed, 24 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/62626/1 diff --git a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb index 599478f..54373c4 100644 --- a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb @@ -1,6 +1,29 @@ # SPDX-License-Identifier: GPL-2.0-or-later fw_config - # TODO define when available + field FORM_FACTOR 0 + option FORM_FACTOR_CLAMSHELL 0 + option FORM_FACTOR_CONVERTIBLE 1 + end + field FP 1 + option FP_ABSENT 0 + option FP_PRESENT 1 + end + field WLAN 2 3 + option WLAN_MT7921LE 0 + option WLAN_RTL8852 1 + end + field WWAN 4 5 + option WWAN_DIASABLED 0 + option WWAN_FM101GL 1 + end + field IO_DB 6 7 + option IO_DB_A1_PS8811_C1_PS8818 0 + option IO_DB_A1_None_C1_ANX7483QN 1 + end + field AUDIO_DB 8 9 + option AUDIO_DB_C_ALC5682I_A_ALC1019 0 + option AUDIO_DB_C_NAU88L25YGB_A_MAX98360AENL 1 + end end chip soc/amd/sabrina -- To view, visit https://review.coreboot.org/c/coreboot/+/62626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6bb3f717b3d30fe5f166dfc958024e931a070c8 Gerrit-Change-Number: 62626 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: commonlib/bsd: Remove cb_err_t
by Yu-Ping Wu (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Jakub Czapiga, Julius Werner, Tim Wawrzynczak, Felix Held. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62600 ) Change subject: commonlib/bsd: Remove cb_err_t ...................................................................... Patch Set 1: (4 comments) File payloads/libpayload/tests/libcbfs/cbfs-verification-test.c: https://review.coreboot.org/c/coreboot/+/62600/comment/334afa7d_d418ad92 PS1, Line 63: size_t *data_offset_out, struct vb2_hash *metadata_hash) Indentation. File src/commonlib/bsd/cbfs_mcache.c: https://review.coreboot.org/c/coreboot/+/62600/comment/d517d9cb_f1ed10a2 PS1, Line 44: size_t already_read, void *arg) Indentation. File src/commonlib/bsd/cbfs_private.c: https://review.coreboot.org/c/coreboot/+/62600/comment/790a5fd1_80f38f93 PS1, Line 7: const size_t devsize) Indentation. File src/soc/qualcomm/sc7180/display/dsi.c: https://review.coreboot.org/c/coreboot/+/62600/comment/8549c76a_b66a7d98 PS1, Line 207: static enum cb_err mdss_dsi_send_init_cmd(enum mipi_dsi_transaction type, const u8 *body, u8 len) > line over 96 characters Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/62600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaec36210d129db26d51f0a105d3de070c03b686b Gerrit-Change-Number: 62600 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 07 Mar 2022 03:13:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya/var/kinox: Modify the DPTF/Fan parameters
by Dtrain Hsu (Code Review) 07 Mar '22

07 Mar '22

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62625 ) Change subject: mb/google/brya/var/kinox: Modify the DPTF/Fan parameters ...................................................................... mb/google/brya/var/kinox: Modify the DPTF/Fan parameters Follow the Thermal_paramters_list v1.0 to modify DPTF/Fan parameters. BUG=b:221180425, b:222020226, b:221182596 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I5f44120430029130d38b89d0eab6bbf205aca929 --- M src/mainboard/google/brya/variants/kinox/overridetree.cb 1 file changed, 141 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/62625/1 diff --git a/src/mainboard/google/brya/variants/kinox/overridetree.cb b/src/mainboard/google/brya/variants/kinox/overridetree.cb index 958d692..829a291 100644 --- a/src/mainboard/google/brya/variants/kinox/overridetree.cb +++ b/src/mainboard/google/brya/variants/kinox/overridetree.cb @@ -46,6 +46,147 @@ }" device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM_SOC"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[3].desc" = ""WWAN"" + + # TODO: below values are initial reference values only + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(80, 97), + TEMP_PCT(65, 93), + TEMP_PCT(58, 86), + TEMP_PCT(50, 80), + TEMP_PCT(45, 64), + TEMP_PCT(43, 52), + TEMP_PCT(40, 47), + TEMP_PCT(35, 40), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(75, 97), + TEMP_PCT(70, 93), + TEMP_PCT(60, 86), + TEMP_PCT(52, 80), + TEMP_PCT(47, 64), + TEMP_PCT(43, 52), + TEMP_PCT(40, 47), + TEMP_PCT(35, 40), + } + }, + [2] = { + .target = DPTF_TEMP_SENSOR_2, + .thresholds = { + TEMP_PCT(75, 97), + TEMP_PCT(70, 93), + TEMP_PCT(60, 86), + TEMP_PCT(52, 80), + TEMP_PCT(47, 64), + TEMP_PCT(43, 52), + TEMP_PCT(40, 47), + TEMP_PCT(35, 40), + } + }, + [3] = { + .target = DPTF_TEMP_SENSOR_3, + .thresholds = { + TEMP_PCT(75, 97), + TEMP_PCT(70, 93), + TEMP_PCT(60, 86), + TEMP_PCT(52, 80), + TEMP_PCT(47, 64), + TEMP_PCT(43, 52), + TEMP_PCT(40, 47), + TEMP_PCT(35, 40), + } + }, + [4] = { + .target = DPTF_TEMP_SENSOR_4, + .thresholds = { + TEMP_PCT(75, 97), + TEMP_PCT(70, 93), + TEMP_PCT(60, 86), + TEMP_PCT(52, 80), + TEMP_PCT(47, 64), + TEMP_PCT(43, 52), + TEMP_PCT(40, 47), + TEMP_PCT(35, 40), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 90, 10000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 10000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 90, 10000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 90, 10000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 90, 10000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 90, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 90, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 90, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 15000, + .max_power = 17000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 28 * MSECS_PER_SEC, + .granularity = 500, + }, + .pl2 = { + .min_power = 39000, + .max_power = 39000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end device ref pcie_rp7 on chip drivers/net register "wake" = "GPE0_DW0_07" -- To view, visit https://review.coreboot.org/c/coreboot/+/62625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f44120430029130d38b89d0eab6bbf205aca929 Gerrit-Change-Number: 62625 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in blobs[master]: soc/mediatek/mt8195: Update dram.elf from 1.8.1 to 1.9.1
by Yu-Ping Wu (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/blobs/+/62583 ) Change subject: soc/mediatek/mt8195: Update dram.elf from 1.8.1 to 1.9.1 ...................................................................... Patch Set 1: Verified+1 Code-Review+2 -- To view, visit https://review.coreboot.org/c/blobs/+/62583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: master Gerrit-Change-Id: I05aac544fa3749c6d43dec2df034e1ebe265ebeb Gerrit-Change-Number: 62583 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Comment-Date: Mon, 07 Mar 2022 02:56:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek: Add PCIe support
by Yu-Ping Wu (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Hung-Te Lin, Arthur Heymans, Shelley Chen, Furquan Shaikh, Paul Menzel, Angel Pons, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56791 ) Change subject: soc/mediatek: Add PCIe support ...................................................................... Patch Set 16: Code-Review+2 (1 comment) File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/56791/comment/2e7dfde0_1ebb49db PS11, Line 3: arch > device/mmio.h has been added on line 6. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/56791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 Gerrit-Change-Number: 56791 Gerrit-PatchSet: 16 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Mon, 07 Mar 2022 02:54:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2022