coreboot-gerrit March 2022

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Change in coreboot[master]: mb/google/dedede/var/lantis: Add ELAN touchscreen support for Landrid
by Henry Sun (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Tony Huang, Robert Chen, Shou-Chieh Hsu, Karthik Ramasubramanian. Henry Sun has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62002 ) Change subject: mb/google/dedede/var/lantis: Add ELAN touchscreen support for Landrid ...................................................................... Patch Set 13: Code-Review-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23d3de5e45aa2876c1590a1e09679d652a3f2906 Gerrit-Change-Number: 62002 Gerrit-PatchSet: 13 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 07 Mar 2022 04:08:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/nivviks: Change bluetooth USB2 port from 8 to 10
by Krishna P Bhat D (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Reka Norman. Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62585 ) Change subject: mb/google/brya/var/nivviks: Change bluetooth USB2 port from 8 to 10 ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica2067023125c04fc753eabc944ae29ff59dc864 Gerrit-Change-Number: 62585 Gerrit-PatchSet: 2 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kangheui Won <khwon(a)chromium.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Usha P <usha.p(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 04:06:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: include/devices/pci_ids.h: Rework indentations
by build bot (Jenkins) (Code Review) 07 Mar '22

07 Mar '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61531 ) Change subject: include/devices/pci_ids.h: Rework indentations ...................................................................... Patch Set 8: Verified+1 (1 comment) File src/include/device/pci_ids.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143254): https://review.coreboot.org/c/coreboot/+/61531/comment/75f23ec0_c3420176 PS8, Line 832: #define PCI_DID_PCTECH_SAMURAI_IDE 0x3020 please, no space before tabs -- To view, visit https://review.coreboot.org/c/coreboot/+/61531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I070d5fbeece570aa410637d3b5b2d24137c9401f Gerrit-Change-Number: 61531 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 03:54:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: include/devices/pci_ids.h: Rework indentations
by Felix Singer (Code Review) 07 Mar '22

07 Mar '22

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61531 to look at the new patch set (#8). Change subject: include/devices/pci_ids.h: Rework indentations ...................................................................... include/devices/pci_ids.h: Rework indentations CB:39331 is a tree-wide change trying to reduce the line length when PCI IDs are used. Even if the commands documented in its commit message took care of many resulting spacing issues, some are still left. Thus, rework the remaining spacing issues. Change-Id: I070d5fbeece570aa410637d3b5b2d24137c9401f Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/include/device/pci_ids.h 1 file changed, 961 insertions(+), 961 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/61531/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/61531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I070d5fbeece570aa410637d3b5b2d24137c9401f Gerrit-Change-Number: 61531 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: change loglevel prefix
by Chen Wisley (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Wisley Chen. Hello Wisley Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/62628 to review the following change. Change subject: mb/google/brya: change loglevel prefix ...................................................................... mb/google/brya: change loglevel prefix Change loglevel from "BIOS_ERR" to "BIOS_INFO/BIOS_DEBUG/BIOS_SPEW" BUG=b:222038287 TEST=emerge-bry coreboot Change-Id: I5de038abba235ea5df866c194118143fcf3f7188 Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> --- M src/device/device.c M src/drivers/intel/usb4/retimer/retimer.c M src/ec/google/chromeec/ec_lpc.c M src/ec/google/chromeec/ec_smbios.c M src/mainboard/google/brya/variants/baseboard/brask/ramstage.c M src/soc/intel/alderlake/retimer.c M src/soc/intel/common/block/cse/cse_eop.c 7 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/62628/1 diff --git a/src/device/device.c b/src/device/device.c index 8337d55..9c153ed 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -167,7 +167,7 @@ if (!curdev->ops || !curdev->ops->read_resources) { if (curdev->path.type != DEVICE_PATH_APIC) - printk(BIOS_ERR, "%s missing %s\n", + printk(BIOS_SPEW, "%s missing %s\n", dev_path(curdev), __func__); continue; } @@ -277,7 +277,7 @@ continue; if (!curdev->ops || !curdev->ops->set_resources) { - printk(BIOS_ERR, "%s missing set_resources\n", + printk(BIOS_SPEW, "%s missing set_resources\n", dev_path(curdev)); continue; } diff --git a/src/drivers/intel/usb4/retimer/retimer.c b/src/drivers/intel/usb4/retimer/retimer.c index 0c027eb..58ef2a8 100644 --- a/src/drivers/intel/usb4/retimer/retimer.c +++ b/src/drivers/intel/usb4/retimer/retimer.c @@ -358,7 +358,7 @@ for (dfp_port = 0; dfp_port < DFP_NUM_MAX; dfp_port++) { if (!config->dfp[dfp_port].power_gpio.pin_count) { - printk(BIOS_ERR, "%s: No DFP%1d power GPIO for %s\n", + printk(BIOS_INFO, "%s: No DFP%1d power GPIO for %s\n", __func__, dfp_port, dev_path(dev)); continue; } diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index a82ea5d..52469d4 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -239,7 +239,7 @@ /* Check result */ cec_command->cmd_code = read_byte(EC_LPC_ADDR_HOST_DATA); if (cec_command->cmd_code) { - printk(BIOS_ERR, "EC returned error result code %d\n", + printk(BIOS_INFO, "EC returned error result code %d\n", cec_command->cmd_code); return -i; } diff --git a/src/ec/google/chromeec/ec_smbios.c b/src/ec/google/chromeec/ec_smbios.c index 1ee7283..d62a0a0 100644 --- a/src/ec/google/chromeec/ec_smbios.c +++ b/src/ec/google/chromeec/ec_smbios.c @@ -29,7 +29,7 @@ if (google_chromeec_cbi_get_oem_name(&oem_name[0], ARRAY_SIZE(oem_name)) < 0) { - printk(BIOS_ERR, "Couldn't obtain OEM name from CBI\n"); + printk(BIOS_INFO, "Couldn't obtain OEM name from CBI\n"); manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; } else { manuf = &oem_name[0]; diff --git a/src/mainboard/google/brya/variants/baseboard/brask/ramstage.c b/src/mainboard/google/brya/variants/baseboard/brask/ramstage.c index 9628b44..f80fa6c 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/ramstage.c +++ b/src/mainboard/google/brya/variants/baseboard/brask/ramstage.c @@ -29,7 +29,7 @@ } if (i == ARRAY_SIZE(cpuid_to_adl)) { - printk(BIOS_ERR, "Cannot find correct intel sku index.\n"); + printk(BIOS_DEBUG, "Cannot find correct intel sku index.\n"); return false; } @@ -41,7 +41,7 @@ } if (i == num_entries) { - printk(BIOS_ERR, "Cannot find correct brask sku index.\n"); + printk(BIOS_DEBUG, "Cannot find correct brask sku index.\n"); return false; } diff --git a/src/soc/intel/alderlake/retimer.c b/src/soc/intel/alderlake/retimer.c index 09bf112..3fd9c2d 100644 --- a/src/soc/intel/alderlake/retimer.c +++ b/src/soc/intel/alderlake/retimer.c @@ -18,7 +18,7 @@ for (uint8_t i = 0; i < MAX_TYPE_C_PORTS; i++) { if (i == typec_port) { - printk(BIOS_ERR, "USB Type-C %d mapped to EC port %d\n", typec_port, + printk(BIOS_INFO, "USB Type-C %d mapped to EC port %d\n", typec_port, ec_port); return ec_port; } diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index 3a08a73..4cf7110 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -172,7 +172,7 @@ static bool eop_sent = false; if (eop_sent) { - printk(BIOS_ERR, "EOP already sent\n"); + printk(BIOS_INFO, "EOP already sent\n"); return; } -- To view, visit https://review.coreboot.org/c/coreboot/+/62628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5de038abba235ea5df866c194118143fcf3f7188 Gerrit-Change-Number: 62628 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8195: Enable PCIe support for mt8195
by Hung-Te Lin (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Arthur Heymans, Paul Menzel, Yu-Ping Wu, Jianjun Wang. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56793 ) Change subject: soc/mediatek/mt8195: Enable PCIe support for mt8195 ...................................................................... Patch Set 18: (1 comment) File src/soc/mediatek/mt8195/Kconfig: https://review.coreboot.org/c/coreboot/+/56793/comment/7ee403ad_e81d107d PS8, Line 13: select PCIE_MEDIATEK > hungte@, do you prefer enabling PCI in mainboard Kconfig? That really depends on how we organize the initialization. One typical solution is - Always select the config in SoC, since it's always available - But don't do init by default in SoC folder, and leave it to the mainboard to decide if it wants to init. On the otherhand, if there's no easy way to do that (e.g., there are lots of init steps must be done inside other init steps so we can't easily decide it from mainboard), then I'd agree to move the option into mainboard. From the change here, I can't easily identify which is the case - will things go wrong if we select PCI, and support pci_domain_ops, but don't really enable PCI? -- To view, visit https://review.coreboot.org/c/coreboot/+/56793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I314572955f1021abe9f2f0f4635670135ed08fff Gerrit-Change-Number: 56793 Gerrit-PatchSet: 18 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Mon, 07 Mar 2022 03:49:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

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Change in blobs[master]: soc/mediatek/mt8195: Update dram.elf from 1.8.1 to 1.9.1
by Rex-BC Chen (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/blobs/+/62583 ) Change subject: soc/mediatek/mt8195: Update dram.elf from 1.8.1 to 1.9.1 ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: update commit message: Cq-Depend: chromium:3504704 -- To view, visit https://review.coreboot.org/c/blobs/+/62583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: master Gerrit-Change-Id: I05aac544fa3749c6d43dec2df034e1ebe265ebeb Gerrit-Change-Number: 62583 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 03:44:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: include/devices/pci_ids.h: Rework indentations
by Felix Singer (Code Review) 07 Mar '22

07 Mar '22

Felix Singer has uploaded a new patch set (#7). ( https://review.coreboot.org/c/coreboot/+/61531 ) Change subject: include/devices/pci_ids.h: Rework indentations ...................................................................... include/devices/pci_ids.h: Rework indentations CB:39331 is a tree-wide change trying to reduce the line length when PCI IDs are used. Even if the commands documented in its commit message took care of many resulting spacing issues, some are still left. Thus, rework the remaining spacing issues. Change-Id: I070d5fbeece570aa410637d3b5b2d24137c9401f Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/include/device/pci_ids.h 1 file changed, 961 insertions(+), 961 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/61531/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/61531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I070d5fbeece570aa410637d3b5b2d24137c9401f Gerrit-Change-Number: 61531 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: include/devices/pci_ids.h: Rework indentations
by build bot (Jenkins) (Code Review) 07 Mar '22

07 Mar '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61531 ) Change subject: include/devices/pci_ids.h: Rework indentations ...................................................................... Patch Set 6: (1 comment) File src/include/device/pci_ids.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143252): https://review.coreboot.org/c/coreboot/+/61531/comment/b7dbe203_40182e54 PS6, Line 832: #define PCI_DID_PCTECH_SAMURAI_IDE 0x3020 please, no space before tabs -- To view, visit https://review.coreboot.org/c/coreboot/+/61531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I070d5fbeece570aa410637d3b5b2d24137c9401f Gerrit-Change-Number: 61531 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 03:35:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: include/devices/pci_ids.h: Rework indentations
by Felix Singer (Code Review) 07 Mar '22

07 Mar '22

Felix Singer has uploaded a new patch set (#6). ( https://review.coreboot.org/c/coreboot/+/61531 ) Change subject: include/devices/pci_ids.h: Rework indentations ...................................................................... include/devices/pci_ids.h: Rework indentations CB:39331 is a tree-wide change trying to reduce the line length when PCI IDs are used. Even if the used commands documented in its commit message took care of many resulting spacing issues, some are still left. Thus, rework the remaining spacing issues. Change-Id: I070d5fbeece570aa410637d3b5b2d24137c9401f Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/include/device/pci_ids.h 1 file changed, 961 insertions(+), 961 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/61531/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/61531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I070d5fbeece570aa410637d3b5b2d24137c9401f Gerrit-Change-Number: 61531 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2022