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Change subject: mb/google/brya: Disable C state auto demotion for Brya & Brask
......................................................................
mb/google/brya: Disable C state auto demotion for Brya & Brask
C state auto demotion feature allows hardware to determine C state as
per platform policy. Since Brya sets performance policy to balanced from
hardware, auto demotion can be disabled without performance impact.
Also, disabling this feature results in 110 mW power savings during
video playback.
BUG=b:221876248
BRANCH=firmware-brya-14505.B
TEST=Code compiles and correct value of C state auto demotion is passed
to FSP. Also power and performance impact has been measure by respective
teams.
Change-Id: I41eea916cdfe4a86e4d263e3191f5cb40fa33a90
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com>
---
M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
2 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/62630/5
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Change subject: device/mmio.h: Move readXp/writeXp helpers to device/mmio.h
......................................................................
device/mmio.h: Move readXp/writeXp helpers to device/mmio.h
These helpers are not architecture dependent and it might be used for
different platform.
Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com>
Change-Id: Ic13a94d91affb7cf65a2f22f08ea39ed671bc8e8
---
M src/acpi/acpi.c
M src/arch/arm/include/armv4/arch/mmio.h
M src/arch/arm/include/armv7/arch/mmio.h
M src/arch/x86/include/arch/mmio.h
M src/include/device/mmio.h
M src/security/intel/cbnt/logging.c
M src/soc/intel/common/block/smm/smihandler.c
7 files changed, 71 insertions(+), 49 deletions(-)
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Change subject: soc/intel/adl: Send EOP early in the boot sequence
......................................................................
soc/intel/adl: Send EOP early in the boot sequence
As part of boot time optimization, one of the culprit was CSE where
response to End Of Post (EOP) command used to take ~60ms. Earlier patch
was pushed to delay the EOP to reduce response time to ~5-7 ms. During
this stage overall platform boot time was ~1.15 seconds.
Once boot time was optimized to ~ 1 seconds, CSE EOP time again
increased to ~80 ms since coreboot used to send EOP at the time where
CSE was busy. This created some back and forth moving of sending EOP
command function within coreboot sequence.
Upon debugging using traces, it was found that coreboot used to send
EOP late where CSE was busy loading other IP payload, so it might take
more time to respond.
In order to avoid delayed response, coreboot has to send EOP in
stage when CSE is done with firmware init and it will be ready to
serve EOP as soon as possible. This also aligns with previous flow where
FSP used to send EOP once silicon init is done and coreboot used to
rely on FSP to send this message.
Moving EOP to earlier stage (From SoC) meets the requirement and CSE EOP time
reduces from ~60 ms to ~20 ms on Brya board.
Note that once SoC code sends EOP, coreboot common code won't send it
again since common code already has check in case EOP is sent earlier.
BUG=b:211085685
BRANCH=None
TEST=Tested on Brya system before and after the changes. Observed ~40ms
savings in boot time.
Change-Id: I9401d5e36ad43cdc0dfe947aabc82528d824df9b
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com>
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/chip.c
2 files changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/62272/6
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Change subject: libpayload: Parse DDR information through coreboot tables
......................................................................
Patch Set 35:
(1 comment)
File src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h:
https://review.coreboot.org/c/coreboot/+/59193/comment/c7a014d3_d4e20a7a
PS32, Line 13: dram_info
> Done
The file is still called mem_chip_info.h, while the struct is called mem_chip.
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Change subject: intel/block/cpu: Keep flash region cached until the payload is loaded
......................................................................
Set Ready For Review
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Change subject: soc/intel/alderlake: Allow mainboard to configure C state auto-demotion
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/62629/comment/94a8aba2_a626ad1e
PS2, Line 721: /
> The comment is not very useful. Please remove.
Ack
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Change subject: mb/google/brya: Disable C state auto demotion for Brya
......................................................................
Patch Set 3: Code-Review+1
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Change subject: soc/intel/alderlake: Allow mainboard to configure C state auto-demotion
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/62629/comment/0f806574_2172d457
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Change subject: mb/google/brya: Disable C state auto demotion for Brya
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62630/comment/a1e1d846_ca222dd3
PS1, Line 13: video
> Move to next line
Done
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