coreboot-gerrit March 2022

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Change in coreboot[master]: mb/google/brya/var/kinox: Enable PCIe-eMMC bridge
by Felix Singer (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Dtrain Hsu, Tim Wawrzynczak. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62631 ) Change subject: mb/google/brya/var/kinox: Enable PCIe-eMMC bridge ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec34708e5879c47f5339c48fd996eb6d7ef0ee86 Gerrit-Change-Number: 62631 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 06:45:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/kinox: Enable PCIe-eMMC bridge
by Dtrain Hsu (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Dtrain Hsu, Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62631 to look at the new patch set (#2). Change subject: mb/google/brya/var/kinox: Enable PCIe-eMMC bridge ...................................................................... mb/google/brya/var/kinox: Enable PCIe-eMMC bridge Enable PCIe-eMMC bridge for Kinox. BUG=b:218786363, b:211176722 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: Iec34708e5879c47f5339c48fd996eb6d7ef0ee86 --- M src/mainboard/google/brya/variants/kinox/gpio.c M src/mainboard/google/brya/variants/kinox/overridetree.cb 2 files changed, 18 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/62631/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec34708e5879c47f5339c48fd996eb6d7ef0ee86 Gerrit-Change-Number: 62631 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Retry END_OF_POST command
by Sridhar Siricilla (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Anil Kumar K, Subrata Banik, Tim Wawrzynczak, Michael Niewöhner, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62192 ) Change subject: soc/intel/common: Retry END_OF_POST command ...................................................................... Patch Set 9: (1 comment) File src/soc/intel/common/block/cse/cse_eop.c: https://review.coreboot.org/c/coreboot/+/62192/comment/ba901e23_ddada14a PS9, Line 142: cse_send_end_of_post_message > suggestion: what about […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/62192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaec4d5564e3d962c1cc866351e9e7eaa8e58683 Gerrit-Change-Number: 62192 Gerrit-PatchSet: 9 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 06:44:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Retry END_OF_POST command
by Sridhar Siricilla (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Anil Kumar K, Subrata Banik, Michael Niewöhner, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62192 ) Change subject: soc/intel/common: Retry END_OF_POST command ...................................................................... Patch Set 9: (3 comments) Patchset: PS9: > Tested on out-of-tree Clevo L140MU (TGL): […] @Michael, Thanks for checking. Do you have system which shows reported EOP issue? or did you simulate the issue to try the EOP retry CL? File src/soc/intel/common/block/cse/cse_eop.c: https://review.coreboot.org/c/coreboot/+/62192/comment/f8c246bb_f6ec665b PS9, Line 102: printk(BIOS_ERR, "HECI: EOP send/receive fail\n"); > note: we are dropping this serial msg now? handle_cse_eop_result() logs the error message, hence it was removed. https://review.coreboot.org/c/coreboot/+/62192/comment/2aecc6cd_295b30f2 PS9, Line 144: size_t retry > nit: move inside for loop itself? Outside of for loop still should be fine! -- To view, visit https://review.coreboot.org/c/coreboot/+/62192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaec4d5564e3d962c1cc866351e9e7eaa8e58683 Gerrit-Change-Number: 62192 Gerrit-PatchSet: 9 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 06:43:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/kinox: Enable PCIe-eMMC bridge for Kinox
by Felix Singer (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Dtrain Hsu, Tim Wawrzynczak. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62631 ) Change subject: mb/google/brya/var/kinox: Enable PCIe-eMMC bridge for Kinox ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62631/comment/dbd6469b_6d4a98da PS1, Line 7: for Kinox Remove this. It's mentioned in the prefix. -- To view, visit https://review.coreboot.org/c/coreboot/+/62631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec34708e5879c47f5339c48fd996eb6d7ef0ee86 Gerrit-Change-Number: 62631 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 06:32:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/kinox: Enable PCIe-eMMC bridge for Kinox
by Dtrain Hsu (Code Review) 07 Mar '22

07 Mar '22

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62631 ) Change subject: mb/google/brya/var/kinox: Enable PCIe-eMMC bridge for Kinox ...................................................................... mb/google/brya/var/kinox: Enable PCIe-eMMC bridge for Kinox Enable PCIe-eMMC bridge for Kinox. BUG=b:218786363, b:211176722 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: Iec34708e5879c47f5339c48fd996eb6d7ef0ee86 --- M src/mainboard/google/brya/variants/kinox/gpio.c M src/mainboard/google/brya/variants/kinox/overridetree.cb 2 files changed, 18 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/62631/1 diff --git a/src/mainboard/google/brya/variants/kinox/gpio.c b/src/mainboard/google/brya/variants/kinox/gpio.c index 0fbfee0..fa63c1d 100644 --- a/src/mainboard/google/brya/variants/kinox/gpio.c +++ b/src/mainboard/google/brya/variants/kinox/gpio.c @@ -41,7 +41,7 @@ /* D17 : UART1_RXD ==> NC */ PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG), /* D18 : UART1_TXD ==> EMMC_PE_RST_L */ - PAD_CFG_GPO_LOCK(GPP_D18, 1, LOCK_CONFIG), + PAD_CFG_GPO(GPP_D18, 1, DEEP), /* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */ /* E4 : SATA_DEVSLP0 ==> USB_A1_RT_RST_ODL */ @@ -93,6 +93,8 @@ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* D18 : UART1_TXD ==> EMMC_PE_RST_L */ + PAD_CFG_GPO(GPP_D18, 0, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), /* F14 : GSXDIN ==> EN_PP3300_SSD */ @@ -107,7 +109,7 @@ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), - /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + /* H13 : I2C7_SCL ==> EN_PP3300_EMMC */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* CPU PCIe VGPIO for PEG60 */ diff --git a/src/mainboard/google/brya/variants/kinox/overridetree.cb b/src/mainboard/google/brya/variants/kinox/overridetree.cb index 829a291..c6b3789 100644 --- a/src/mainboard/google/brya/variants/kinox/overridetree.cb +++ b/src/mainboard/google/brya/variants/kinox/overridetree.cb @@ -187,6 +187,20 @@ device generic 0 alias dptf_policy on end end end + device ref pcie_rp6 on + # Enable PCIe-to-eMMC bridge PCIE 6 using clk 1 + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" + register "srcclk_pin" = "1" + device generic 0 alias emmc_rtd3 on end + end + end # BH799BBLN device ref pcie_rp7 on chip drivers/net register "wake" = "GPE0_DW0_07" -- To view, visit https://review.coreboot.org/c/coreboot/+/62631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec34708e5879c47f5339c48fd996eb6d7ef0ee86 Gerrit-Change-Number: 62631 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/i210: Set log level to BIOS_NOTICE on missing MAC address
by Werner Zeh (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Paul Menzel, Patrick Rudolph. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62008 ) Change subject: drivers/intel/i210: Set log level to BIOS_NOTICE on missing MAC address ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62008/comment/f243d6bc_b418f31e PS1, Line 12: > I still think the second case is an error, as the user would expect the MAC address to be used from […] I have rephrased the message a bit to make clear that the MAC address stored in the MAC will be uesed if the mainboard does not provide an address. -- To view, visit https://review.coreboot.org/c/coreboot/+/62008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibfc58845f0ea47ced048b446e685c4860a29f075 Gerrit-Change-Number: 62008 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 05:56:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: device/mmio.h: Move readXp/writeXp helpers to device/mmio.h
by Jianjun Wang (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Lance Zhao, Arthur Heymans, Tim Wawrzynczak, Julius Werner, Angel Pons, Patrick Rudolph, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62561 ) Change subject: device/mmio.h: Move readXp/writeXp helpers to device/mmio.h ...................................................................... Patch Set 5: (1 comment) File src/arch/arm/include/armv4/arch/mmio.h: https://review.coreboot.org/c/coreboot/+/62561/comment/3ee1640f_1d2d1c9a PS4, Line 27: static inline uint64_t read64(const void *addr) > Could we call die("Not supported") here? Good idea. -- To view, visit https://review.coreboot.org/c/coreboot/+/62561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic13a94d91affb7cf65a2f22f08ea39ed671bc8e8 Gerrit-Change-Number: 62561 Gerrit-PatchSet: 5 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 05:55:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/i210: Set log level to BIOS_NOTICE on missing MAC address
by Werner Zeh (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Werner Zeh, Patrick Rudolph. Hello build bot (Jenkins), Paul Menzel, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62008 to look at the new patch set (#2). Change subject: drivers/intel/i210: Set log level to BIOS_NOTICE on missing MAC address ...................................................................... drivers/intel/i210: Set log level to BIOS_NOTICE on missing MAC address Set the log level to BIOS_NOTICE for the case where the mainboard can not provide a MAC address since this can be a valid case. Showing this message with log level BIOS_ERR is not appropriate. In addition, rephrase the message to make clear that if the mainboard does not provide a MAC address the one stored in the MAC will be used. Change-Id: Ibfc58845f0ea47ced048b446e685c4860a29f075 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/drivers/intel/i210/i210.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/62008/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibfc58845f0ea47ced048b446e685c4860a29f075 Gerrit-Change-Number: 62008 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8195: Enable PCIe support for mt8195
by Yu-Ping Wu (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Hung-Te Lin, Arthur Heymans, Paul Menzel. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56793 ) Change subject: soc/mediatek/mt8195: Enable PCIe support for mt8195 ...................................................................... Patch Set 18: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56793/comment/bf34b487_3a302f0b PS18, Line 7: for mt8195 Can be removed. File src/soc/mediatek/mt8195/Kconfig: https://review.coreboot.org/c/coreboot/+/56793/comment/9aad5a23_b5b4fbc5 PS8, Line 13: select PCIE_MEDIATEK > On the other hand, if there's no easy way to do that CB:62360, which actually enables PCI, is done using coreboot device tree (at least from the patch chain that is the only mainboard CL). I'm not sure if we want to have a devicetree.cb per board. -- To view, visit https://review.coreboot.org/c/coreboot/+/56793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I314572955f1021abe9f2f0f4635670135ed08fff Gerrit-Change-Number: 56793 Gerrit-PatchSet: 18 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 05:54:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit March 2022