coreboot-gerrit March 2022

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Change in coreboot[master]: mb/google/brya: Disable C state auto demotion for Brya & Brask
by Subrata Banik (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Vinay Kumar, Maulik V Vaghela, Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62630 ) Change subject: mb/google/brya: Disable C state auto demotion for Brya & Brask ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62630/comment/8092fec8_87b8426c PS5, Line 9: C state > Done I could see there are other `C state` which also need modification. -- To view, visit https://review.coreboot.org/c/coreboot/+/62630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41eea916cdfe4a86e4d263e3191f5cb40fa33a90 Gerrit-Change-Number: 62630 Gerrit-PatchSet: 6 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.corp-partner.google.com> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.corp-partner.google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 08:14:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Disable C state auto demotion for Brya & Brask
by Subrata Banik (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Vinay Kumar, Maulik V Vaghela, Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62630 ) Change subject: mb/google/brya: Disable C state auto demotion for Brya & Brask ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62630/comment/fa357088_a2c3d849 PS5, Line 13: disabling this feature results in 110 mW power savings > Yes, no performance impact was seen with disabling autodemotion. Isn't that surprising? if I go by the current observation from your side about no perf impact and good power savings by disabling the C-state auto demotion/promotion, then what is the usefulness of this feature. Ideally this feature would provide better energy conservation when enable. -- To view, visit https://review.coreboot.org/c/coreboot/+/62630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41eea916cdfe4a86e4d263e3191f5cb40fa33a90 Gerrit-Change-Number: 62630 Gerrit-PatchSet: 6 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.corp-partner.google.com> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.corp-partner.google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 08:14:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Vinay Kumar <vinay.kumar(a)intel.corp-partner.google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: commonlib/bsd: Remove cb_err_t
by Jakub Czapiga (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Julius Werner, Tim Wawrzynczak, Felix Held. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62600 ) Change subject: commonlib/bsd: Remove cb_err_t ...................................................................... Patch Set 1: (6 comments) File payloads/libpayload/libc/fmap.c: https://review.coreboot.org/c/coreboot/+/62600/comment/edd2aaf6_f0e8aa00 PS1, Line 42: size_t *size) Indentation. File payloads/libpayload/tests/libcbfs/cbfs-lookup-test.c: https://review.coreboot.org/c/coreboot/+/62600/comment/d47b2e61_2bb28f3e PS1, Line 60: union cbfs_mdata *mdata_out, size_t *data_offset_out) Indentation. https://review.coreboot.org/c/coreboot/+/62600/comment/1e74d435_88e093d6 PS1, Line 91: size_t *data_offset_out, struct vb2_hash *metadata_hash) Indentation. File payloads/libpayload/tests/libcbfs/cbfs-verification-test.c: https://review.coreboot.org/c/coreboot/+/62600/comment/83f72fb7_ef35a92f PS1, Line 57: union cbfs_mdata *mdata_out, size_t *data_offset_out) Indentation. File src/drivers/parade/ps8640/ps8640.c: https://review.coreboot.org/c/coreboot/+/62600/comment/da2fc209_215610e9 PS1, Line 84: static enum cb_err ps8640_bridge_aux_request(uint8_t bus, : uint8_t chip, : unsigned int target_reg, : unsigned int total_size, : enum aux_request request, : uint8_t *data) nit: Can it be changed to occupy less lines? File src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c: https://review.coreboot.org/c/coreboot/+/62600/comment/abe7b3d6_37d83623 PS1, Line 158: static enum cb_err sn65dsi86_bridge_aux_request(uint8_t bus, : uint8_t chip, : unsigned int target_reg, : unsigned int total_size, : enum aux_request request, : uint8_t *data) nit: Can it be changed to occupy less lines? -- To view, visit https://review.coreboot.org/c/coreboot/+/62600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaec36210d129db26d51f0a105d3de070c03b686b Gerrit-Change-Number: 62600 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 07 Mar 2022 08:11:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Disable C state auto demotion for Brya & Brask
by Vinay Kumar (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak. Vinay Kumar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62630 ) Change subject: mb/google/brya: Disable C state auto demotion for Brya & Brask ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62630/comment/6dce7a20_fbae4563 PS5, Line 13: disabling this feature results in 110 mW power savings > Yes Subrata, Performance impact has been measured using the CL (disabling autodemotion) and there is […] Yes, no performance impact was seen with disabling autodemotion. -- To view, visit https://review.coreboot.org/c/coreboot/+/62630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41eea916cdfe4a86e4d263e3191f5cb40fa33a90 Gerrit-Change-Number: 62630 Gerrit-PatchSet: 6 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 08:04:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/cbmem: add an option to append timestamp
by Mattias Nissler (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Julius Werner. Mattias Nissler has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62639 ) Change subject: util/cbmem: add an option to append timestamp ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Julius, per discussion on the bug, here's a stab at extending cbmem so it can append timestamps. -- To view, visit https://review.coreboot.org/c/coreboot/+/62639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic99e5a11d8cc3f9fffae8eaf2787652105cf4842 Gerrit-Change-Number: 62639 Gerrit-PatchSet: 1 Gerrit-Owner: Mattias Nissler <mnissler(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 08:02:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/cbmem: add an option to append timestamp
by Mattias Nissler (Code Review) 07 Mar '22

07 Mar '22

Mattias Nissler has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62639 ) Change subject: util/cbmem: add an option to append timestamp ...................................................................... util/cbmem: add an option to append timestamp Add an option to the cbmem utility that can be used to append an entry to the cbmem timestamp table from userspace. This is useful for bookkeeping of post-coreboot timing information while still being able to use cbmem-based tooling for processing the generated data. BUG=b:217638034 BRANCH=none TEST=Manual, invoke new cbmem option, then verify that cbmem -t shows the added timestamp. Change-Id: Ic99e5a11d8cc3f9fffae8eaf2787652105cf4842 Signed-off-by: Mattias Nissler <mnissler(a)chromium.org> --- M util/cbmem/cbmem.c 1 file changed, 78 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/62639/1 diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index a39ef2a..72c7017 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -79,9 +79,9 @@ } /* Return mapping of physical address requested. */ -static const void *mapping_virt(const struct mapping *mapping) +static void *mapping_virt(const struct mapping *mapping) { - const char *v = mapping->virt; + char *v = mapping->virt; if (v == NULL) return NULL; @@ -90,8 +90,8 @@ } /* Returns virtual address on success, NULL on error. mapping is filled in. */ -static const void *map_memory(struct mapping *mapping, unsigned long long phys, - size_t sz) +static void *map_memory_with_prot(struct mapping *mapping, + unsigned long long phys, size_t sz, int prot) { void *v; unsigned long long page_size; @@ -113,7 +113,7 @@ phys); } - v = mmap(NULL, mapping->virt_size, PROT_READ, MAP_SHARED, mem_fd, + v = mmap(NULL, mapping->virt_size, prot, MAP_SHARED, mem_fd, phys - mapping->offset); if (v == MAP_FAILED) { @@ -131,6 +131,14 @@ return mapping_virt(mapping); } +/* Convenience helper for the common case of read-only mappings. */ +static const void *map_memory(struct mapping *mapping, unsigned long long phys, + size_t sz) +{ + return map_memory_with_prot(mapping, phys, sz, PROT_READ); +} + + /* Returns 0 on success, < 0 on error. mapping is cleared if successful. */ static int unmap_memory(struct mapping *mapping) { @@ -528,6 +536,16 @@ } } +static uint64_t timestamp_get(void) +{ +#if defined(__x86_64__) + return __rdtsc(); +#else + fprintf(stderr, + "Don't know how to obtain timestamps on this platform.\n"); +#endif +} + static const char *timestamp_name(uint32_t id) { for (size_t i = 0; i < ARRAY_SIZE(timestamp_ids); i++) { @@ -537,6 +555,15 @@ return "<unknown>"; } +static uint32_t timestamp_name_to_id(const char *name) +{ + for (size_t i = 0; i < ARRAY_SIZE(timestamp_ids); i++) { + if (!strcmp(timestamp_ids[i].name, name)) + return timestamp_ids[i].id; + } + return 0; +} + static uint64_t timestamp_print_parseable_entry(uint32_t id, uint64_t stamp, uint64_t prev_stamp) { @@ -673,6 +700,38 @@ free(sorted_tst_p); } +/* add a timestamp entry */ +static void timestamp_add_now(uint32_t timestamp_id) +{ + struct timestamp_table *tst_p; + struct mapping timestamp_mapping; + + if (timestamps.tag != LB_TAG_TIMESTAMPS) { + fprintf(stderr, "No timestamps found in coreboot table.\n"); + return; + } + + tst_p = map_memory_with_prot(&timestamp_mapping, timestamps.cbmem_addr, + timestamps.size, PROT_READ | PROT_WRITE); + if (!tst_p) + die("Unable to map timestamp table\n"); + + /* + * Note that coreboot sizes the cbmem entry in the table according to + * max_entries, so it's OK to just add more entries if there's room. + */ + if (tst_p->num_entries >= tst_p->max_entries) { + fprintf(stderr, "Not enough space to add timestamp.\n"); + } else { + int64_t time = timestamp_get() - tst_p->base_time; + tst_p->entries[tst_p->num_entries].entry_id = timestamp_id; + tst_p->entries[tst_p->num_entries].entry_stamp = time; + tst_p->num_entries += 1; + } + + unmap_memory(&timestamp_mapping); +} + /* dump the tcpa log table */ static void dump_tcpa_log(void) { @@ -1304,6 +1363,7 @@ unsigned int rawdump_id = 0; int max_loglevel = BIOS_NEVER; int print_unknown_logs = 1; + uint32_t timestamp_id = 0; int opt, option_index = 0; static struct option long_options[] = { @@ -1316,6 +1376,7 @@ {"tcpa-log", 0, 0, 'L'}, {"timestamps", 0, 0, 't'}, {"parseable-timestamps", 0, 0, 'T'}, + {"add-timestamp", required_argument, 0, 'a'}, {"hexdump", 0, 0, 'x'}, {"rawdump", required_argument, 0, 'r'}, {"verbose", 0, 0, 'V'}, @@ -1323,7 +1384,7 @@ {"help", 0, 0, 'h'}, {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "c12B:CltTLxVvh?r:", + while ((opt = getopt_long(argc, argv, "c12B:CltTa:LxVvh?r:", long_options, &option_index)) != EOF) { switch (opt) { case 'c': @@ -1373,6 +1434,13 @@ machine_readable_timestamps = 1; print_defaults = 0; break; + case 'a': + print_defaults = 0; + timestamp_id = timestamp_name_to_id(optarg); + /* Parse numeric value if name is unknown */ + if (timestamp_id == 0) + timestamp_id = strtoul(optarg, NULL, 10); + break; case 'V': verbose = 1; break; @@ -1395,7 +1463,7 @@ print_usage(argv[0], 1); } - mem_fd = open("/dev/mem", O_RDONLY, 0); + mem_fd = open("/dev/mem", O_RDWR, 0); if (mem_fd < 0) { fprintf(stderr, "Failed to gain memory access: %s\n", strerror(errno)); @@ -1482,6 +1550,9 @@ if (print_rawdump) dump_cbmem_raw(rawdump_id); + if (timestamp_id) + timestamp_add_now(timestamp_id); + if (print_defaults || print_timestamps) dump_timestamps(machine_readable_timestamps); -- To view, visit https://review.coreboot.org/c/coreboot/+/62639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic99e5a11d8cc3f9fffae8eaf2787652105cf4842 Gerrit-Change-Number: 62639 Gerrit-PatchSet: 1 Gerrit-Owner: Mattias Nissler <mnissler(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/variants/felwinter: Fixed stylus UI behavior bug
by EricR Lai (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: John Su, Tim Wawrzynczak, Ricky Chang. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62638 ) Change subject: mb/google/brya/variants/felwinter: Fixed stylus UI behavior bug ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f5e2992584d759eb1a559684d1cda08c7cbe3f2 Gerrit-Change-Number: 62638 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ricky Chang <rickytlchang(a)google.com> Gerrit-Comment-Date: Mon, 07 Mar 2022 07:56:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Allow mainboard to configure C state auto-demotion
by Subrata Banik (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Felix Singer, Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62629 ) Change subject: soc/intel/alderlake: Allow mainboard to configure C state auto-demotion ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/alderlake/chip.h: https://review.coreboot.org/c/coreboot/+/62629/comment/f7464bd1_54aab865 PS4, Line 572: DisableC1StateAutoDemotion > Yes Subrata...I just wanted to align with syntax in entire file. > Let me push another patch correcting entire file, is that okay? Sure. SGTM -- To view, visit https://review.coreboot.org/c/coreboot/+/62629 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d7839d8fecd7b5403f52f3926d1d0bc06728ed9 Gerrit-Change-Number: 62629 Gerrit-PatchSet: 4 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 07:52:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/felwinter: Fixed stylus UI behavior bug
by John Su (Code Review) 07 Mar '22

07 Mar '22

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62638 ) Change subject: mb/google/brya/variants/felwinter: Fixed stylus UI behavior bug ...................................................................... mb/google/brya/variants/felwinter: Fixed stylus UI behavior bug Fixed stylus UI behavior bug. - Configuring GPP_A7 as "ACPI_GPIO_INPUT_ACTIVE_LOW". - Change wakeup_event_action from ASSERTED to DEASSERTED. BUG=b:220992812 TEST=emerge-brya coreboot chromeos-bootimage and verify pass Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: I6f5e2992584d759eb1a559684d1cda08c7cbe3f2 --- M src/mainboard/google/brya/variants/felwinter/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/62638/1 diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index d184276..acd96dd 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -275,10 +275,10 @@ end chip drivers/generic/gpio_keys register "name" = ""PENH"" - register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A7)" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_A7)" register "key.wake_gpe" = "GPE0_DW0_08" register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" - register "key.wakeup_event_action" = "EV_ACT_ASSERTED" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" register "key.dev_name" = ""EJCT"" register "key.linux_code" = "SW_PEN_INSERTED" register "key.linux_input_type" = "EV_SW" -- To view, visit https://review.coreboot.org/c/coreboot/+/62638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f5e2992584d759eb1a559684d1cda08c7cbe3f2 Gerrit-Change-Number: 62638 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/starlabs/merlin: Use ECWR function
by Sean Rhodes (Code Review) 07 Mar '22

07 Mar '22

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62637 ) Change subject: ec/starlabs/merlin: Use ECWR function ...................................................................... ec/starlabs/merlin: Use ECWR function Use ECWR function, instead of writing raw values to emem, to avoid a lack of syncronisation as it uses a mutex. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I90cfd3e1752fe25493bd72ea6bcab1fd9318d2e3 --- M src/ec/starlabs/merlin/acpi/suspend.asl 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/62637/1 diff --git a/src/ec/starlabs/merlin/acpi/suspend.asl b/src/ec/starlabs/merlin/acpi/suspend.asl index 4532f10..bfa6a07 100644 --- a/src/ec/starlabs/merlin/acpi/suspend.asl +++ b/src/ec/starlabs/merlin/acpi/suspend.asl @@ -81,11 +81,11 @@ // 0x01 == Disabled == 0x22 Case (0x00) { - \_SB.PCI0.LPCB.EC.TPLE = 0x00 + ECWR (0x00, TPLE) } Case (0x01) { - \_SB.PCI0.LPCB.EC.TPLE = 0x22 + ECWR (0x22, TPLE) } } @@ -97,11 +97,11 @@ // 0x01 == Enabled == 0xdd Case (0x00) { - \_SB.PCI0.LPCB.EC.KLSE = 0x00 + ECWR (0x00, KLSE) } Case (0x01) { - \_SB.PCI0.LPCB.EC.KLSE = 0xdd + ECWR (0xdd, KLSE) } } @@ -113,19 +113,19 @@ // 0x03 == High == 0xaa Case (0x00) { - \_SB.PCI0.LPCB.EC.KLBE 0xdd + ECWR (0xdd, KLBE) } Case (0x01) { - \_SB.PCI0.LPCB.EC.KLBE = 0xcc + ECWR (0xdd, KLBE) } Case (0x02) { - \_SB.PCI0.LPCB.EC.KLBE = 0xbb + ECWR (0xbb, KLBE) } Case (0x03) { - \_SB.PCI0.LPCB.EC.KLBE = 0xaa + ECWR (0xaa, KLBE) } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/62637 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90cfd3e1752fe25493bd72ea6bcab1fd9318d2e3 Gerrit-Change-Number: 62637 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-MessageType: newchange

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coreboot-gerrit March 2022