coreboot-gerrit March 2022

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Change in coreboot[master]: cbmem: Fix console banner matches
by Yu-Ping Wu (Code Review) 10 Mar '22

10 Mar '22

Attention is currently required from: Julius Werner. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62720 ) Change subject: cbmem: Fix console banner matches ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99fb347eb1cf7b043a2113dfda7c798d6ee38975 Gerrit-Change-Number: 62720 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 10 Mar 2022 01:10:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: console: Add loglevel marker codes to stored consoles
by Julius Werner (Code Review) 10 Mar '22

10 Mar '22

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61308 ) Change subject: console: Add loglevel marker codes to stored consoles ...................................................................... Patch Set 12: (1 comment) File util/cbmem/cbmem.c: https://review.coreboot.org/c/coreboot/+/61308/comment/d8d138b5_b4849b15 PS12, Line 798: coreboot > There will be a BIOS_NOTICE marker before "coreboot". Oops... thanks for noticing, that needs to be fixed. CB:62720 -- To view, visit https://review.coreboot.org/c/coreboot/+/61308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86073f48aaf1e0a58e97676fb80e2475ec418ffc Gerrit-Change-Number: 61308 Gerrit-PatchSet: 12 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 10 Mar 2022 01:00:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: cbmem: Fix console banner matches
by Julius Werner (Code Review) 10 Mar '22

10 Mar '22

Attention is currently required from: Yu-Ping Wu. Hello Yu-Ping Wu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/62720 to review the following change. Change subject: cbmem: Fix console banner matches ...................................................................... cbmem: Fix console banner matches Since the new loglevel markers were added, there will now be a marker character at the beginning of the coreboot banner string, and this will make the existing regular expressions meant to find it fail to match. This patch fixes the problem by just allowing for a single extra character there (any character to avoid the hassle of having to match the marker explicitly). The extra character is optional so that we will still continue to match banners from older versions of coreboot as well. Since the `?` glyph is not available in basic POSIX regular expressions, we have to switch to REG_EXTENDED syntax (should otherwise make no difference). (Also, move side effects out of assert() while I'm here, that's not actually safe for the standard libc implementation.) Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I99fb347eb1cf7b043a2113dfda7c798d6ee38975 --- M util/cbmem/cbmem.c 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/62720/1 diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index a39ef2a..eef68a0 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -818,8 +818,8 @@ cursor = previous = 0; if (type != CONSOLE_PRINT_FULL) { #define BANNER_REGEX(stage) \ - "\n\ncoreboot-[^\n]* " stage " starting.*\\.\\.\\.\n" -#define OVERFLOW_REGEX(stage) "\n\\*\\*\\* Pre-CBMEM " stage " console overflow" + "\n\n.?coreboot-[^\n]* " stage " starting.*\\.\\.\\.\n" +#define OVERFLOW_REGEX(stage) "\n.?\\*\\*\\* Pre-CBMEM " stage " console overflow" const char *regex[] = { BANNER_REGEX("verstage-before-bootblock"), BANNER_REGEX("bootblock"), BANNER_REGEX("verstage"), @@ -831,7 +831,8 @@ for (size_t i = 0; !cursor && i < ARRAY_SIZE(regex); i++) { regex_t re; regmatch_t match; - assert(!regcomp(&re, regex[i], 0)); + int res = regcomp(&re, regex[i], REG_EXTENDED); + assert(res == 0); /* Keep looking for matches so we find the last one. */ while (!regexec(&re, console_c + cursor, 1, &match, 0)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/62720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99fb347eb1cf7b043a2113dfda7c798d6ee38975 Gerrit-Change-Number: 62720 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Add EPP override support
by Cliff Huang (Code Review) 10 Mar '22

10 Mar '22

Attention is currently required from: Selma Bensaid, Patrick Rudolph. Hello build bot (Jenkins), Cliff Huang, Selma Bensaid, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62654 to look at the new patch set (#8). Change subject: soc/intel/alderlake: Add EPP override support ...................................................................... soc/intel/alderlake: Add EPP override support This updates energy performance preference value to all logical CPUs when the corresponding chip config is true. BUG=b:219785001 BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Change-Id: Ie59623fe715b0c545f8d4b6c22ab2ce670a29798 --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/cpu.c 2 files changed, 28 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/62654/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/62654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie59623fe715b0c545f8d4b6c22ab2ce670a29798 Gerrit-Change-Number: 62654 Gerrit-PatchSet: 8 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: libpayload: Parse DDR Information using coreboot tables
by Hung-Te Lin (Code Review) 10 Mar '22

10 Mar '22

Attention is currently required from: Felix Singer, Shelley Chen, Ravi kumar, Paul Menzel, mturney mturney, Julius Werner, Angel Pons, Arthur Heymans, Xixi Chen, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59193 ) Change subject: libpayload: Parse DDR Information using coreboot tables ...................................................................... Patch Set 37: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieca7e9fc0e1a018fcb2e9315aebee088edac858e Gerrit-Change-Number: 59193 Gerrit-PatchSet: 37 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-CC: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Comment-Date: Thu, 10 Mar 2022 00:44:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: (TEST ONLY)mb/google/brya/var/vell: Add 5G WWAN ACPI support for vell
by Robert Chen (Code Review) 10 Mar '22

10 Mar '22

Robert Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62719 ) Change subject: (TEST ONLY)mb/google/brya/var/vell: Add 5G WWAN ACPI support for vell ...................................................................... (TEST ONLY)mb/google/brya/var/vell: Add 5G WWAN ACPI support for vell Add FM350GL 5G WWAN support using drivers/wwan/fm and addtional PM features from RTD3. BUG=b:220084872 TEST=emerge-brya coreboot Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Change-Id: Ica7863b337cd1b55ec3bac771cf9bc774598a95e --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/vell/gpio.c M src/mainboard/google/brya/variants/vell/include/variant/gpio.h M src/mainboard/google/brya/variants/vell/overridetree.cb 4 files changed, 34 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/62719/1 diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 3895aab..dd84075 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -154,10 +154,11 @@ config BOARD_GOOGLE_VELL bool "-> Vell" select BOARD_GOOGLE_BASEBOARD_BRYA + select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_GFX_GENERIC select DRIVERS_INTEL_MIPI_CAMERA + select HAVE_WWAN_POWER_SEQUENCE select SOC_INTEL_COMMON_BLOCK_IPU - select CHROMEOS_WIFI_SAR if CHROMEOS config BOARD_GOOGLE_VOLMAR bool "-> Volmar" diff --git a/src/mainboard/google/brya/variants/vell/gpio.c b/src/mainboard/google/brya/variants/vell/gpio.c index e6588b9..2fa7ae1 100644 --- a/src/mainboard/google/brya/variants/vell/gpio.c +++ b/src/mainboard/google/brya/variants/vell/gpio.c @@ -39,11 +39,17 @@ PAD_CFG_NF_LOCK(GPP_E12, NONE, NF3, LOCK_CONFIG), /* E13 : THC0_SPI1_IO2 ==> UWB_GSPI0_DO */ PAD_CFG_NF_LOCK(GPP_E13, NONE, NF3, LOCK_CONFIG), + /* E16 : RSVD_TP ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_E16, 1, DEEP), /* E22 : DDPA_CTRLCLK ==> WWAN_CONFIG0 */ PAD_CFG_GPI(GPP_E22, NONE, DEEP), /* E23 : DDPA_CTRLDATA ==> USB_C3_OC_ODL */ PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), - + /* + * E0 : SATAXPCIE0 ==> WWAN_PERST_L + * Drive high here, so that PERST_L is sequenced after RST_L + */ + PAD_CFG_GPO(GPP_E0, 1, DEEP), /* F19 : NC */ PAD_NC(GPP_F19, NONE), @@ -94,6 +100,8 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* B4 : PROC_GP3 ==> SSD_PERST_L */ @@ -117,7 +125,8 @@ PAD_CFG_GPO(GPP_D3, 1, DEEP), /* D11 : ISH_SPI_MISO ==> USB_C0_LSX_SOC_TX */ PAD_CFG_NF(GPP_D11, NONE, DEEP, NF4), - + /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */ + PAD_CFG_GPO(GPP_E0, 0, DEEP), /* E3 : PROC_GP0 ==> MEM_STRAP_0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* E5 : SATA_DEVSLP1 ==> MEM_CH_SEL */ @@ -131,6 +140,8 @@ PAD_CFG_GPO(GPP_E16, 0, DEEP), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ @@ -162,6 +173,8 @@ static const struct pad_config romstage_gpio_table[] = { /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */ + PAD_CFG_GPO(GPP_F21, 1, DEEP), }; const struct pad_config *variant_romstage_gpio_table(size_t *num) diff --git a/src/mainboard/google/brya/variants/vell/include/variant/gpio.h b/src/mainboard/google/brya/variants/vell/include/variant/gpio.h index c4fe342..99d09b2 100644 --- a/src/mainboard/google/brya/variants/vell/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/vell/include/variant/gpio.h @@ -5,4 +5,10 @@ #include <baseboard/gpio.h> +#define WWAN_FCPO GPP_F21 +#define WWAN_RST GPP_E16 +#define WWAN_PERST GPP_E0 +#define T1_OFF_MS 16 +#define T2_OFF_MS 2 + #endif diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index 5f2780e..2f4e4af 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -155,6 +155,17 @@ device generic 0 on end end end + device ref pcie_rp6 on + chip drivers/wwan/fm + register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)" + register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)" + register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)" + use rp6_rtd3 as rtd3dev + device generic 0 on + end + end + end device ref pcie_rp8 off end device ref pcie_rp9 off end device ref tcss_dma0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/62719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica7863b337cd1b55ec3bac771cf9bc774598a95e Gerrit-Change-Number: 62719 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TEST]cb_err.h: Add cb_err_t to fix the building error
by Julius Werner (Code Review) 10 Mar '22

10 Mar '22

Attention is currently required from: Bao Zheng, Zheng Bao. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62674 ) Change subject: [TEST]cb_err.h: Add cb_err_t to fix the building error ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Sorry, this was a merge conflict. It should have already been resolved with CB:62676, please update your repository to that. This typedef should not be added back in. -- To view, visit https://review.coreboot.org/c/coreboot/+/62674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94eb73643b16db25faec1dab3f221a70c4e39ac0 Gerrit-Change-Number: 62674 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Wed, 09 Mar 2022 23:26:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/common: Add support for energy performance preference (EPP)
by Felix Held (Code Review) 09 Mar '22

09 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62653 ) Change subject: cpu/intel/common: Add support for energy performance preference (EPP) ...................................................................... cpu/intel/common: Add support for energy performance preference (EPP) This provides support to update energy performance preference value. BUG=b:219785001 BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Change-Id: I381bca6c7746a4ae7ca32aa1b4992a6d53c8eaaa Reviewed-on: https://review.coreboot.org/c/coreboot/+/62653 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/cpu/intel/common/common.h M src/cpu/intel/common/common_init.c M src/include/cpu/x86/msr.h 3 files changed, 66 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h index ef0a5d9..a29fd2e 100644 --- a/src/cpu/intel/common/common.h +++ b/src/cpu/intel/common/common.h @@ -47,4 +47,23 @@ */ void set_energy_perf_bias(u8 policy); +/* + * Check energy performance preference and HWP capabilities from Thermal and + * Power Management Leaf CPUID. + */ +bool check_energy_perf_cap(void); + +/* + * Set the IA32_HWP_REQUEST Energy-Performance Preference bits on the logical + * thread. 0 is a hint to the HWP to prefer performance, and 255 is a hint to + * prefer energy efficiency. + */ +void set_energy_perf_pref(u8 pref); + +/* + * Instructs the CPU to use EPP hints. This means that any energy policies set + * up in `set_energy_perf_bias` will be ignored afterwards. + */ +void enable_energy_perf_pref(void); + #endif diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index 24e3eeb..4d6df84 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -5,9 +5,12 @@ #include <console/console.h> #include <cpu/intel/msr.h> #include <cpu/x86/msr.h> +#include <cpu/intel/turbo.h> #include "common.h" -#define CPUID_6_ECX_EPB (1 << 3) +#define CPUID_6_ECX_EPB (1 << 3) +#define CPUID_6_ENGERY_PERF_PREF (1 << 10) +#define CPUID_6_HWP (1 << 7) void set_vmx_and_lock(void) { @@ -182,3 +185,43 @@ msr_unset_and_set(IA32_ENERGY_PERF_BIAS, ENERGY_POLICY_MASK, epb); printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", epb); } + +/* + * Check energy performance preference and HWP capabilities from Thermal and + * Power Management Leaf CPUID + */ +bool check_energy_perf_cap(void) +{ + const u32 cap = cpuid_eax(CPUID_LEAF_PM); + if (!(cap & CPUID_6_ENGERY_PERF_PREF)) + return false; + if (!(cap & CPUID_6_HWP)) + return false; + return true; +} + +/* + * Instructs the CPU to use EPP hints. This means that any energy policies set + * up in `set_energy_perf_bias` will be ignored afterwards. + */ +void enable_energy_perf_pref(void) +{ + msr_t msr = rdmsr(IA32_PM_ENABLE); + if (!(msr.lo & HWP_ENABLE)) { + /* Package-scoped MSR */ + printk(BIOS_DEBUG, "HWP_ENABLE: energy-perf preference in favor of energy-perf bias\n"); + msr_set(IA32_PM_ENABLE, HWP_ENABLE); + } +} + +/* + * Set the IA32_HWP_REQUEST Energy-Performance Preference bits on the logical + * thread. 0 is a hint to the HWP to prefer performance, and 255 is a hint to + * prefer energy efficiency. + * This function needs to be called when HWP_ENABLE is set. +*/ +void set_energy_perf_pref(u8 pref) +{ + msr_unset_and_set(IA32_HWP_REQUEST, IA32_HWP_REQUEST_EPP_MASK, + pref << IA32_HWP_REQUEST_EPP_SHIFT); +} diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 4d1cb68..9f30c05 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -86,8 +86,11 @@ #define IA32_VMX_MISC_MSR 0x485 #define IA32_PM_ENABLE 0x770 +#define HWP_ENABLE 0x1 #define IA32_HWP_CAPABILITIES 0x771 #define IA32_HWP_REQUEST 0x774 +#define IA32_HWP_REQUEST_EPP_MASK 0xff000000 +#define IA32_HWP_REQUEST_EPP_SHIFT 24 #define IA32_HWP_STATUS 0x777 #define IA32_L3_PROTECTED_WAYS 0xc85 #define IA32_SF_QOS_INFO 0xc87 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62653 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I381bca6c7746a4ae7ca32aa1b4992a6d53c8eaaa Gerrit-Change-Number: 62653 Gerrit-PatchSet: 5 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Retry MEI CSE DISABLE command
by Tim Wawrzynczak (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Sridhar Siricilla, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62560 ) Change subject: soc/intel/common: Retry MEI CSE DISABLE command ...................................................................... Patch Set 5: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62560/comment/5954c082_087a928c PS5, Line 12: same here, mention it's from the BWG? -- To view, visit https://review.coreboot.org/c/coreboot/+/62560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id38a172d670a0cd44643744f27b85ca7e368ccdb Gerrit-Change-Number: 62560 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.nest(a)gmail.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 09 Mar 2022 22:47:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Retry END_OF_POST command
by Tim Wawrzynczak (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Anil Kumar K, Sridhar Siricilla, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62192 ) Change subject: soc/intel/common: Retry END_OF_POST command ...................................................................... Patch Set 11: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62192/comment/1440376c_e85b4f59 PS11, Line 12: nit: can you mention that this is from the BWG? -- To view, visit https://review.coreboot.org/c/coreboot/+/62192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaec4d5564e3d962c1cc866351e9e7eaa8e58683 Gerrit-Change-Number: 62192 Gerrit-PatchSet: 11 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.nest(a)gmail.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 09 Mar 2022 22:46:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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