coreboot-gerrit March 2022

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Change in coreboot[master]: libpayload: Parse DDR Information using coreboot tables
by Xixi Chen (Code Review) 10 Mar '22

10 Mar '22

Attention is currently required from: Felix Singer, Shelley Chen, Ravi kumar, Paul Menzel, mturney mturney, Ravi Kumar Bokka, Angel Pons, Arthur Heymans. Xixi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59193 ) Change subject: libpayload: Parse DDR Information using coreboot tables ...................................................................... Patch Set 37: (1 comment) File src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h: https://review.coreboot.org/c/coreboot/+/59193/comment/a484ae9b_51099c34 PS35, Line 10: MEM_CHIP_LPDDR4 > Done Yes, means adding MEM_CHIP_LPDDR4X, i saw it on latest patchset. -- To view, visit https://review.coreboot.org/c/coreboot/+/59193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieca7e9fc0e1a018fcb2e9315aebee088edac858e Gerrit-Change-Number: 59193 Gerrit-PatchSet: 37 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-CC: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-CC: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Comment-Date: Thu, 10 Mar 2022 01:55:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Comment-In-Reply-To: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/primus{4es}: add eMMC enable pin in ramstage
by Casper Chang (Code Review) 10 Mar '22

10 Mar '22

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62703 to look at the new patch set (#2). Change subject: mb/google/brya/var/primus{4es}: add eMMC enable pin in ramstage ...................................................................... mb/google/brya/var/primus{4es}: add eMMC enable pin in ramstage Program BayHub eMMC enable pin in ram stage to prevent baseboad override the setting leads RTD3 not able to control when enter and exit suspend state. BUG=b:222436260 TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage scope enable pin while performing suspend stress and enable pin works as expected. test suspend stress 1000 cycles passed on primus. Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Change-Id: I1b6f164cc326bd368addb1e143ad2cbd449bb08d --- M src/mainboard/google/brya/variants/primus/gpio.c M src/mainboard/google/brya/variants/primus4es/gpio.c 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/62703/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b6f164cc326bd368addb1e143ad2cbd449bb08d Gerrit-Change-Number: 62703 Gerrit-PatchSet: 2 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: libpayload: Parse DDR Information using coreboot tables
by Julius Werner (Code Review) 10 Mar '22

10 Mar '22

Attention is currently required from: Felix Singer, Shelley Chen, Ravi kumar, Paul Menzel, mturney mturney, Angel Pons, Arthur Heymans, Xixi Chen. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59193 ) Change subject: libpayload: Parse DDR Information using coreboot tables ...................................................................... Patch Set 37: (2 comments) File payloads/libpayload/libc/coreboot.c: https://review.coreboot.org/c/coreboot/+/59193/comment/efb599fd_e1934213 PS37, Line 263: _INFO If we remove the "info" everywhere else it should be removed here as well. File src/commonlib/bsd/include/commonlib/bsd/mem_chip.h: https://review.coreboot.org/c/coreboot/+/59193/comment/8b45355f_2bb583ab PS37, Line 7: MEM_CHIP_DDR3 = 1, nit: do we maybe wanna make this a little more organized? e.g. something like DDR3 = 0x30, LPDDR3 = 0x38, DDR4 = 0x40, LPDDR4 = 0x48, LPDDR4x = 0x49 -- To view, visit https://review.coreboot.org/c/coreboot/+/59193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieca7e9fc0e1a018fcb2e9315aebee088edac858e Gerrit-Change-Number: 59193 Gerrit-PatchSet: 37 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-CC: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-CC: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Comment-Date: Thu, 10 Mar 2022 01:51:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/nissa/var/nivviks: Add GL9750 power sequence
by Eric Lai (Code Review) 10 Mar '22

10 Mar '22

Eric Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62722 ) Change subject: mb/google/nissa/var/nivviks: Add GL9750 power sequence ...................................................................... mb/google/nissa/var/nivviks: Add GL9750 power sequence Select GL9750 driver and add power sequence. BUG=b:223304292 TEST=check GL9750 can get enumerate by kernel. 01:00.0 SD Host controller: Genesys Logic, Inc Device 9750 (rev 01) Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: Ib6d461a56f6aeba30994daafe8993c36df4b309d --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/nivviks/gpio.c 2 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/62722/1 diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 3895aab..8052a90 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -83,6 +83,7 @@ config BOARD_GOOGLE_NIVVIKS bool "-> Nivviks" select BOARD_GOOGLE_BASEBOARD_NISSA + select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_INTEL_MIPI_CAMERA select HAVE_WWAN_POWER_SEQUENCE diff --git a/src/mainboard/google/brya/variants/nivviks/gpio.c b/src/mainboard/google/brya/variants/nivviks/gpio.c index f0700ab..a5f9cb8 100644 --- a/src/mainboard/google/brya/variants/nivviks/gpio.c +++ b/src/mainboard/google/brya/variants/nivviks/gpio.c @@ -31,6 +31,8 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* H12 : UART0_RTS# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H12, 0, DEEP), /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ @@ -45,6 +47,13 @@ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : UART0_CTS# ==> EN_PP3300_SD_X */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* H12 : UART0_RTS# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H12, 1, DEEP), }; const struct pad_config *variant_gpio_override_table(size_t *num) @@ -58,3 +67,10 @@ *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/62722 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6d461a56f6aeba30994daafe8993c36df4b309d Gerrit-Change-Number: 62722 Gerrit-PatchSet: 1 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Add IOE P2SB for TCSS
by John Zhao (Code Review) 10 Mar '22

10 Mar '22

Attention is currently required from: Patrick Rudolph. Hello Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62721 to look at the new patch set (#2). Change subject: soc/intel/common: Add IOE P2SB for TCSS ...................................................................... soc/intel/common: Add IOE P2SB for TCSS Meteor Lake has the IOE Die for TCSS. This change adds the IOE P2SB sideband access and exposes API for TCSS usage. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Change-Id: I01f551b6e1f50ebdc1cef2ceee815a492030db19 Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/p2sb.h M src/soc/intel/common/block/p2sb/Kconfig M src/soc/intel/common/block/p2sb/Makefile.inc A src/soc/intel/common/block/p2sb/ioe_p2sb.c M src/soc/intel/common/block/p2sb/p2sb.c 5 files changed, 74 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/62721/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01f551b6e1f50ebdc1cef2ceee815a492030db19 Gerrit-Change-Number: 62721 Gerrit-PatchSet: 2 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Add IOE P2SB for TCSS
by build bot (Jenkins) (Code Review) 10 Mar '22

10 Mar '22

Attention is currently required from: Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62721 ) Change subject: soc/intel/common: Add IOE P2SB for TCSS ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/p2sb/ioe_p2sb.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143678): https://review.coreboot.org/c/coreboot/+/62721/comment/e78b6f03_17d85153 PS1, Line 21: p2sb_dev_sbi_write( PCI_DEV_IOE_P2SB, pid, reg, val); space prohibited after that open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/62721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01f551b6e1f50ebdc1cef2ceee815a492030db19 Gerrit-Change-Number: 62721 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 10 Mar 2022 01:34:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add IOE P2SB for TCSS
by John Zhao (Code Review) 10 Mar '22

10 Mar '22

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62721 ) Change subject: soc/intel/common: Add IOE P2SB for TCSS ...................................................................... soc/intel/common: Add IOE P2SB for TCSS Meteor Lake has the IOE Die for TCSS. This change adds the IOE P2SB sideband access and exposes API for TCSS usage. Change-Id: I01f551b6e1f50ebdc1cef2ceee815a492030db19 Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/p2sb.h M src/soc/intel/common/block/p2sb/Kconfig M src/soc/intel/common/block/p2sb/Makefile.inc A src/soc/intel/common/block/p2sb/ioe_p2sb.c M src/soc/intel/common/block/p2sb/p2sb.c 5 files changed, 74 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/62721/1 diff --git a/src/soc/intel/common/block/include/intelblocks/p2sb.h b/src/soc/intel/common/block/include/intelblocks/p2sb.h index b330ccd..b8aa5bc 100644 --- a/src/soc/intel/common/block/include/intelblocks/p2sb.h +++ b/src/soc/intel/common/block/include/intelblocks/p2sb.h @@ -29,6 +29,10 @@ void p2sb_enable_bar(void); void p2sb_configure_hpet(void); +void ioe_p2sb_enable_bar(void); +uint32_t ioe_p2sb_sbi_read(uint8_t pid, uint16_t reg); +void ioe_p2sb_sbi_write(uint8_t pid, uint16_t reg, uint32_t val); + union p2sb_bdf { struct { uint16_t fn : 3; diff --git a/src/soc/intel/common/block/p2sb/Kconfig b/src/soc/intel/common/block/p2sb/Kconfig index 7f292cd..eedc583 100644 --- a/src/soc/intel/common/block/p2sb/Kconfig +++ b/src/soc/intel/common/block/p2sb/Kconfig @@ -3,3 +3,9 @@ depends on SOC_INTEL_COMMON_BLOCK_PCR help Intel Processor common P2SB driver + +config SOC_INTEL_COMMON_BLOCK_IOE_P2SB + def_bool n + depends on SOC_INTEL_COMMON_BLOCK_PCR + help + Intel Processor common IOE P2SB driver diff --git a/src/soc/intel/common/block/p2sb/Makefile.inc b/src/soc/intel/common/block/p2sb/Makefile.inc index 5c6378e..d9ea0b8 100644 --- a/src/soc/intel/common/block/p2sb/Makefile.inc +++ b/src/soc/intel/common/block/p2sb/Makefile.inc @@ -6,3 +6,9 @@ smm-y += p2sb.c smm-y += p2sblib.c endif + +ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_IOE_P2SB),y) +bootblock-y += ioe_p2sb.c +ramstage-y += ioe_p2sb.c +ramstage-y += p2sblib.c +endif diff --git a/src/soc/intel/common/block/p2sb/ioe_p2sb.c b/src/soc/intel/common/block/p2sb/ioe_p2sb.c new file mode 100644 index 0000000..312ec37 --- /dev/null +++ b/src/soc/intel/common/block/p2sb/ioe_p2sb.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define __SIMPLE_DEVICE__ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <intelblocks/p2sb.h> +#include <intelblocks/p2sblib.h> +#include <intelblocks/pcr.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> + +uint32_t ioe_p2sb_sbi_read(uint8_t pid, uint16_t reg) +{ + return p2sb_dev_sbi_read(PCI_DEV_IOE_P2SB, pid, reg); +} + +void ioe_p2sb_sbi_write(uint8_t pid, uint16_t reg, uint32_t val) +{ + p2sb_dev_sbi_write( PCI_DEV_IOE_P2SB, pid, reg, val); +} + +void ioe_p2sb_enable_bar(void) +{ + /* Enable PCR Base address */ + pci_write_config32(PCI_DEV_IOE_P2SB, PCI_BASE_ADDRESS_0, + (uint32_t)IOE_P2SB_BAR); + pci_write_config32(PCI_DEV_IOE_P2SB, PCI_BASE_ADDRESS_1, + (uint32_t)(IOE_P2SB_BAR >> 32)); + + /* Enable P2SB MSE */ + pci_write_config16(PCI_DEV_IOE_P2SB, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); +} + +static void read_resources(struct device *dev) +{ + mmio_resource(dev, 0, IOE_P2SB_BAR / KiB, IOE_P2SB_SIZE / KiB); +} + +struct device_operations device_ops = { + .read_resources = read_resources, + .set_resources = noop_set_resources, + .ops_pci = &pci_dev_ops_pci, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_MTL_IOE_M_P2SB, + PCI_DID_INTEL_MTL_IOE_P_P2SB, + 0, +}; + +static const struct pci_driver ioe_p2sb __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 94db33d..ef3b88e 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -145,8 +145,6 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_SOC_P2SB, - PCI_DID_INTEL_MTL_IOE_M_P2SB, - PCI_DID_INTEL_MTL_IOE_P_P2SB, PCI_DID_INTEL_APL_P2SB, PCI_DID_INTEL_GLK_P2SB, PCI_DID_INTEL_LWB_P2SB, -- To view, visit https://review.coreboot.org/c/coreboot/+/62721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01f551b6e1f50ebdc1cef2ceee815a492030db19 Gerrit-Change-Number: 62721 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TEST]cb_err.h: Add cb_err_t to fix the building error
by Bao Zheng (Code Review) 10 Mar '22

10 Mar '22

Bao Zheng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/62674 ) Change subject: [TEST]cb_err.h: Add cb_err_t to fix the building error ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/62674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94eb73643b16db25faec1dab3f221a70c4e39ac0 Gerrit-Change-Number: 62674 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/google/brask/variants/moli: init overridetree for moli
by Raihow Shi (Code Review) 10 Mar '22

10 Mar '22

Attention is currently required from: YH Lin, Tim Wawrzynczak, Johnny Li, Zhuohao Lee, Felix Held. Raihow Shi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62321 ) Change subject: mb/google/brask/variants/moli: init overridetree for moli ...................................................................... Patch Set 24: (1 comment) File src/mainboard/google/brya/variants/moli/overridetree.cb: https://review.coreboot.org/c/coreboot/+/62321/comment/b29394b1_25ebf7fc PS22, Line 2: field OB 3 4 : option HDMI 0 : option DP 1 : end > Hi Zhuohao […] done -- To view, visit https://review.coreboot.org/c/coreboot/+/62321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8829d4b39d48ae574eeccbfc62e79b671211ae2d Gerrit-Change-Number: 62321 Gerrit-PatchSet: 24 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 10 Mar 2022 01:19:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Parse DDR Information using coreboot tables
by Yu-Ping Wu (Code Review) 10 Mar '22

10 Mar '22

Attention is currently required from: Felix Singer, Shelley Chen, Ravi kumar, Paul Menzel, mturney mturney, Julius Werner, Angel Pons, Arthur Heymans, Xixi Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59193 ) Change subject: libpayload: Parse DDR Information using coreboot tables ...................................................................... Patch Set 37: Code-Review+1 (2 comments) File src/commonlib/bsd/include/commonlib/bsd/mem_chip.h: https://review.coreboot.org/c/coreboot/+/59193/comment/90a58daa_155ecabf PS37, Line 3: _INFO Remove INFO https://review.coreboot.org/c/coreboot/+/59193/comment/7e3f5f65_994b050a PS37, Line 28: INFO Remove INFO. -- To view, visit https://review.coreboot.org/c/coreboot/+/59193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieca7e9fc0e1a018fcb2e9315aebee088edac858e Gerrit-Change-Number: 59193 Gerrit-PatchSet: 37 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-CC: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-CC: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Comment-Date: Thu, 10 Mar 2022 01:13:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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