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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/alderlake: Inject CSE TS into CBMEM timestamp table
......................................................................
soc/intel/alderlake: Inject CSE TS into CBMEM timestamp table
Get boot performance timestamps from CSE and inject them into CBMEM
timestamp table after normalizing to the zero-point value. Although
consumer CSE sku also supports this feature, it was validated on
CSE Lite sku only.
BUG=b:182575295
TEST=Able to see TS elapse prior to IA reset on Brya/Redrix
990:CSME ROM started execution 0
944:CSE sent 'Boot Stall Done' to PMC 88,000
945:CSE started to handle ICC configuration 88,000 (0)
946:CSE sent 'Host BIOS Prep Done' to PMC 90,000 (2,000)
947:CSE received 'CPU Reset Done Ack sent' from PMC 282,000 (192,000)
0:1st timestamp 330,857 (48,857)
11:start of bootblock 341,811 (10,953)
12:end of bootblock 349,299 (7,487)
Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com>
Change-Id: Idcdbb69538ca2977cd97ce1ef9b211ff6510a3f8
---
M src/soc/intel/alderlake/romstage/romstage.c
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/Makefile.inc
A src/soc/intel/common/block/cse/telemetry.c
M src/soc/intel/common/block/include/intelblocks/cse.h
5 files changed, 92 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/59507/19
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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62165 )
Change subject: mb/google/skyrim: Configure WLAN
......................................................................
Patch Set 30:
(1 comment)
File src/mainboard/google/skyrim/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/62165/comment/371e68a7_7849dd64
PS30, Line 161: WLAN_DISABLE
> Raul, do we need to enable WLAN before DXIO training or PCIe training. […]
We need to enable before PCIe training, so you are right it doesn't make a difference. I got confused and though this was the `AUX_RESET_L`.
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Change subject: soc/intel/alderlake: Inject CSE TS into CBMEM timestamp table
......................................................................
Patch Set 18: Code-Review+2
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Change subject: mb/google/skyrim: Configure WLAN
......................................................................
Patch Set 30:
(2 comments)
File src/mainboard/google/skyrim/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/62165/comment/32d2887b_e7a53311
PS30, Line 161: WLAN_DISABLE
> May be needed for boot time later, not needed now.
Raul, do we need to enable WLAN before DXIO training or PCIe training. I believe DXIO training happens in SMU FW and PCIe training happens in romstage. Please correct me if I am wrong.
If we need to do it before PCIe training then bootblock or early GPIO does not make any difference. If we need to do it before DXIO training, then early GPIO table makes sense.
https://review.coreboot.org/c/coreboot/+/62165/comment/a287c710_b4dce7de
PS30, Line 180: PAD_NFO
> Needed on previous program due to how interrupts were tied together, but not on Skyrim. […]
Same comment as above.
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Change subject: mb/google/brya/var/kinox: update overridetree
......................................................................
Patch Set 9: Code-Review+1
(1 comment)
File src/mainboard/google/brya/variants/kinox/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/62553/comment/5d682368_c9486ff7
PS9, Line 135: ACPI_PLD_GROUP
Can you please look into the `custom_pld` and assocaited properties in other brya variants and use that convention as well? ex: https://review.coreboot.org/c/coreboot/+/62321/24/src/mainboard/google/brya…
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Hello Raul Rangel, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62717
to look at the new patch set (#3).
Change subject: mb/google/skyrim:Update GPIO 32
......................................................................
mb/google/skyrim:Update GPIO 32
GPIO 32 was not allocated correctly, updating to reflect the native
function use of the pin
BUG=b:214412172
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
Change-Id: Idadd2a802b3244eba8ee83f80d8f10baebe4ca40
---
M src/mainboard/google/skyrim/variants/baseboard/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/62717/3
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Hello Raul Rangel, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62717
to look at the new patch set (#2).
Change subject: mb/google/skyrim:Update GPIO 32
......................................................................
mb/google/skyrim:Update GPIO 32
GPIO 32 was not allocated correctly, updating to reflect the native
function use of the pin
BUG=b:223650635
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
Change-Id: Idadd2a802b3244eba8ee83f80d8f10baebe4ca40
---
M src/mainboard/google/skyrim/variants/baseboard/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/62717/2
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