coreboot-gerrit March 2022

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Change in coreboot[master]: soc/amd/*/lpc: rename SPIROM_BASE_ADDRESS_REGISTER
by Felix Held (Code Review) 09 Mar '22

09 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62578 ) Change subject: soc/amd/*/lpc: rename SPIROM_BASE_ADDRESS_REGISTER ...................................................................... soc/amd/*/lpc: rename SPIROM_BASE_ADDRESS_REGISTER Rename SPIROM_BASE_ADDRESS_REGISTER to SPI_BASE_ADDRESS_REGISTER to clarify that this isn't the address the SPI flash gets mapped, but the address of the SPI controller MMIO region. This also aligns the register name with the PPR. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ifd9f98bd01b1c7197b80d642a45657c97f708bcd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62578 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk(a)gmail.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/cezanne/include/soc/lpc.h M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/common/block/lpc/lpc_util.c M src/soc/amd/picasso/include/soc/lpc.h M src/soc/amd/sabrina/include/soc/lpc.h M src/soc/amd/stoneyridge/include/soc/lpc.h 6 files changed, 15 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Jason Glenesk: Looks good to me, but someone else must approve Fred Reitberger: Looks good to me, but someone else must approve diff --git a/src/soc/amd/cezanne/include/soc/lpc.h b/src/soc/amd/cezanne/include/soc/lpc.h index 123a13f..084159e 100644 --- a/src/soc/amd/cezanne/include/soc/lpc.h +++ b/src/soc/amd/cezanne/include/soc/lpc.h @@ -9,7 +9,7 @@ #define LPC_LDRQ0_PU_EN BIT(10) #define LPC_LDRQ0_PD_EN BIT(9) -#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 +#define SPI_BASE_ADDRESS_REGISTER 0xa0 #define SPI_BASE_ALIGNMENT BIT(8) #define SPI_BASE_RESERVED (BIT(5) | BIT(6) | BIT(7)) #define PSP_SPI_MMIO_SEL BIT(4) diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index ee8f7e4..99f84fa 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -124,9 +124,9 @@ /* Special case. The SpiRomEnable and other enables should STAY set. */ res = find_resource(dev, 2); - spi_enable_bits = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER); + spi_enable_bits = pci_read_config32(dev, SPI_BASE_ADDRESS_REGISTER); spi_enable_bits &= SPI_BASE_ALIGNMENT - 1; - pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, + pci_write_config32(dev, SPI_BASE_ADDRESS_REGISTER, res->base | spi_enable_bits); pci_dev_set_resources(dev); diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index 7291959..53bd090 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -187,13 +187,13 @@ u32 base, enables; /* Make sure the base address is predictable */ - base = pci_read_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER); + base = pci_read_config32(_LPCB_DEV, SPI_BASE_ADDRESS_REGISTER); enables = base & SPI_PRESERVE_BITS; base &= ~(SPI_PRESERVE_BITS | SPI_BASE_RESERVED); if (!base) { base = SPI_BASE_ADDRESS; - pci_write_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER, + pci_write_config32(_LPCB_DEV, SPI_BASE_ADDRESS_REGISTER, base | enables | SPI_ROM_ENABLE); /* PCI_COMMAND_MEMORY is read-only and enabled. */ } @@ -233,8 +233,8 @@ /* Route TPM accesses to SPI */ u32 spibase = pci_read_config32(_LPCB_DEV, - SPIROM_BASE_ADDRESS_REGISTER); - pci_write_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER, spibase + SPI_BASE_ADDRESS_REGISTER); + pci_write_config32(_LPCB_DEV, SPI_BASE_ADDRESS_REGISTER, spibase | ROUTE_TPM_2_SPI); } @@ -310,7 +310,7 @@ { u32 base; - base = pci_read_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER); + base = pci_read_config32(_LPCB_DEV, SPI_BASE_ADDRESS_REGISTER); base = ALIGN_DOWN(base, SPI_BASE_ALIGNMENT); return (uintptr_t)base; } @@ -319,12 +319,12 @@ { uint32_t reg32; - reg32 = pci_read_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER); + reg32 = pci_read_config32(_LPCB_DEV, SPI_BASE_ADDRESS_REGISTER); reg32 &= SPI_BASE_ALIGNMENT - 1; /* preserve only reserved, enables */ reg32 |= ALIGN_DOWN(base, SPI_BASE_ALIGNMENT); - pci_write_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER, reg32); + pci_write_config32(_LPCB_DEV, SPI_BASE_ADDRESS_REGISTER, reg32); } void lpc_enable_spi_rom(uint32_t enable) @@ -334,12 +334,12 @@ /* only two types of CS# enables are allowed */ enable &= SPI_ROM_ENABLE | SPI_ROM_ALT_ENABLE; - reg32 = pci_read_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER); + reg32 = pci_read_config32(_LPCB_DEV, SPI_BASE_ADDRESS_REGISTER); reg32 &= ~(SPI_ROM_ENABLE | SPI_ROM_ALT_ENABLE); reg32 |= enable; - pci_write_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER, reg32); + pci_write_config32(_LPCB_DEV, SPI_BASE_ADDRESS_REGISTER, reg32); } static void lpc_enable_controller(void) diff --git a/src/soc/amd/picasso/include/soc/lpc.h b/src/soc/amd/picasso/include/soc/lpc.h index 2705f2d..24d12b3 100644 --- a/src/soc/amd/picasso/include/soc/lpc.h +++ b/src/soc/amd/picasso/include/soc/lpc.h @@ -3,7 +3,7 @@ #ifndef AMD_PICASSO_LPC_H #define AMD_PICASSO_LPC_H -#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 +#define SPI_BASE_ADDRESS_REGISTER 0xa0 #define SPI_BASE_ALIGNMENT BIT(8) #define SPI_BASE_RESERVED (BIT(5) | BIT(6) | BIT(7)) #define PSP_SPI_MMIO_SEL BIT(4) diff --git a/src/soc/amd/sabrina/include/soc/lpc.h b/src/soc/amd/sabrina/include/soc/lpc.h index d5e5712..f0a9257 100644 --- a/src/soc/amd/sabrina/include/soc/lpc.h +++ b/src/soc/amd/sabrina/include/soc/lpc.h @@ -11,7 +11,7 @@ #define LPC_LDRQ0_PU_EN BIT(10) #define LPC_LDRQ0_PD_EN BIT(9) -#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 +#define SPI_BASE_ADDRESS_REGISTER 0xa0 #define SPI_BASE_ALIGNMENT BIT(8) #define SPI_BASE_RESERVED (BIT(5) | BIT(6) | BIT(7)) #define PSP_SPI_MMIO_SEL BIT(4) diff --git a/src/soc/amd/stoneyridge/include/soc/lpc.h b/src/soc/amd/stoneyridge/include/soc/lpc.h index 55e39cc..7d0ffd4 100644 --- a/src/soc/amd/stoneyridge/include/soc/lpc.h +++ b/src/soc/amd/stoneyridge/include/soc/lpc.h @@ -3,7 +3,7 @@ #ifndef AMD_STONEYRIDGE_LPC_H #define AMD_STONEYRIDGE_LPC_H -#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 +#define SPI_BASE_ADDRESS_REGISTER 0xa0 #define SPI_BASE_ALIGNMENT BIT(6) #define SPI_BASE_RESERVED (BIT(4) | BIT(5)) #define ROUTE_TPM_2_SPI BIT(3) -- To view, visit https://review.coreboot.org/c/coreboot/+/62578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd9f98bd01b1c7197b80d642a45657c97f708bcd Gerrit-Change-Number: 62578 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: [Debug][Do not merge]redrix: set SlewRate to SLEW_FAST_2
by Anil Kumar K (Code Review) 09 Mar '22

09 Mar '22

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62714 ) Change subject: [Debug][Do not merge]redrix: set SlewRate to SLEW_FAST_2 ...................................................................... [Debug][Do not merge]redrix: set SlewRate to SLEW_FAST_2 Change-Id: Ief394b601a86633f42dfce512cab1e4e8e18f3e7 --- M src/mainboard/google/brya/variants/redrix/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/62714/1 diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index 3f9c81d..3b9860b 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -38,8 +38,8 @@ # Acoustic settings register "AcousticNoiseMitigation" = "1" - register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" - register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_2" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_2" register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/62714 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief394b601a86633f42dfce512cab1e4e8e18f3e7 Gerrit-Change-Number: 62714 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/skyrim: Add ACPI configuration for USB ports
by Felix Held (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Jon Murphy. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62153 ) Change subject: mb/google/skyrim: Add ACPI configuration for USB ports ...................................................................... Patch Set 37: (1 comment) File src/mainboard/google/skyrim/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/62153/comment/d7af1e9a_3c8a31aa PS37, Line 79: 2.3 > ok, i'll push a patch to change that usb port id. […] CB:62713 -- To view, visit https://review.coreboot.org/c/coreboot/+/62153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1b05f190f25dca1566e1023011cc70c2d32f461 Gerrit-Change-Number: 62153 Gerrit-PatchSet: 37 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Comment-Date: Wed, 09 Mar 2022 18:58:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: qualcomm/sc7280: Add display external clock support in coreboot
by Ravi Kumar Bokka (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Shelley Chen, Ravi kumar, Taniya Das, Sudheer Amrabadi. Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59611 ) Change subject: qualcomm/sc7280: Add display external clock support in coreboot ...................................................................... Patch Set 24: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59611/comment/650ca1d8_852b3f37 PS17, Line 13: 216687885 > syntax should be: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6872ede515401e95ea2dadc9766e3e70fb66144 Gerrit-Change-Number: 59611 Gerrit-PatchSet: 24 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Taniya Das <tdas(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Comment-Date: Wed, 09 Mar 2022 18:58:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/googe/skyrim/baseboard/devicetree: update USB port device ID on xhci2
by Felix Held (Code Review) 09 Mar '22

09 Mar '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62713 ) Change subject: mb/googe/skyrim/baseboard/devicetree: update USB port device ID on xhci2 ...................................................................... mb/googe/skyrim/baseboard/devicetree: update USB port device ID on xhci2 The one USB2 port on the XHCI2 controller should have the port ID 2.0, since it's the first USB2 port on that XHCI controller. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I4a370132960939bccec4eb69a6590d0880b04137 --- M src/mainboard/google/skyrim/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/62713/1 diff --git a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb index c802868..c8897b5 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb @@ -122,7 +122,7 @@ register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_10)" - device usb 2.3 alias usb2_port5 on end + device usb 2.0 alias usb2_port5 on end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/62713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a370132960939bccec4eb69a6590d0880b04137 Gerrit-Change-Number: 62713 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/skyrim: Add ACPI configuration for USB ports
by Felix Held (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Jon Murphy. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62153 ) Change subject: mb/google/skyrim: Add ACPI configuration for USB ports ...................................................................... Patch Set 37: (1 comment) File src/mainboard/google/skyrim/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/62153/comment/fc9318b2_7351feb9 PS37, Line 79: 2.3 > You are right. It should be 2.0. Here is the port enumeration code: https://source.chromium. […] ok, i'll push a patch to change that usb port id. there are 3 new pci ids for the 3 xhci controllers: #define PCI_DID_AMD_FAM17H_MODELA0H_XHCI0 0x1503 #define PCI_DID_AMD_FAM17H_MODELA0H_XHCI1 0x1504 #define PCI_DID_AMD_FAM17H_MODELA0H_XHCI2 0x1505 -- To view, visit https://review.coreboot.org/c/coreboot/+/62153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1b05f190f25dca1566e1023011cc70c2d32f461 Gerrit-Change-Number: 62153 Gerrit-PatchSet: 37 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Comment-Date: Wed, 09 Mar 2022 18:55:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/*/lpc: rename SPIROM_BASE_ADDRESS_REGISTER
by Raul Rangel (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62578 ) Change subject: soc/amd/*/lpc: rename SPIROM_BASE_ADDRESS_REGISTER ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd9f98bd01b1c7197b80d642a45657c97f708bcd Gerrit-Change-Number: 62578 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 09 Mar 2022 18:54:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/chausie/devicetree: enable GFX HDA, ACP and XHCI2 devices
by Raul Rangel (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62571 ) Change subject: mb/amd/chausie/devicetree: enable GFX HDA, ACP and XHCI2 devices ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I186797a832470eb17752e06aa2fcc0b5c9db0398 Gerrit-Change-Number: 62571 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 09 Mar 2022 18:53:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/chausie/devicetree: enable GFX HDA, ACP and XHCI2 devices
by Felix Held (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62571 ) Change subject: mb/amd/chausie/devicetree: enable GFX HDA, ACP and XHCI2 devices ...................................................................... Patch Set 2: (1 comment) File src/mainboard/amd/chausie/devicetree.cb: https://review.coreboot.org/c/coreboot/+/62571/comment/cf77253a_0a133d0b PS1, Line 80: xhci_2 > Did you want to add an ACPI chip driver? […] good catch; added that -- To view, visit https://review.coreboot.org/c/coreboot/+/62571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I186797a832470eb17752e06aa2fcc0b5c9db0398 Gerrit-Change-Number: 62571 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Wed, 09 Mar 2022 18:53:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/chausie/devicetree: enable GFX HDA, ACP and XHCI2 devices
by Felix Held (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Marshall Dawson, Felix Held. Hello Jason Glenesk, build bot (Jenkins), Marshall Dawson, Fred Reitberger, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62571 to look at the new patch set (#2). Change subject: mb/amd/chausie/devicetree: enable GFX HDA, ACP and XHCI2 devices ...................................................................... mb/amd/chausie/devicetree: enable GFX HDA, ACP and XHCI2 devices GFX HDA is the audio controller that provides audio output via the external display connection, ACP is the audio coporcessor for the on- board audio codec and XHCI2 is the third XHCI controller that provides one USB 2.0 port. All those devices are used, so enable them in the board's devicetree. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I186797a832470eb17752e06aa2fcc0b5c9db0398 --- M src/mainboard/amd/chausie/devicetree.cb 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/62571/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I186797a832470eb17752e06aa2fcc0b5c9db0398 Gerrit-Change-Number: 62571 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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