coreboot-gerrit March 2022

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Change in coreboot[master]: drivers/wifi,soc/intel/adl: Move CnviDdrRfim property to drivers
by Tim Wawrzynczak (Code Review) 09 Mar '22

09 Mar '22

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61638 ) Change subject: drivers/wifi,soc/intel/adl: Move CnviDdrRfim property to drivers ...................................................................... drivers/wifi,soc/intel/adl: Move CnviDdrRfim property to drivers Some non-SoC code might want to know whether or not the CNVi DDR RFIM feature is enabled. Also note that future SoCs may also support this feature. To make the CnviDdrRfim property generic, move it from soc/intel/alderlake to drivers/wifi/generic instead. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Idf9fba0a79d1f431269be5851b026ed966600160 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61638 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Reviewed-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> --- M src/drivers/wifi/generic/Makefile.inc M src/drivers/wifi/generic/chip.h M src/drivers/wifi/generic/generic.c A src/drivers/wifi/generic/wifi.h M src/mainboard/google/brya/variants/brya0/overridetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/romstage/fsp_params.c 7 files changed, 55 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Rizwan Qureshi: Looks good to me, approved Varshit B Pandya: Looks good to me, but someone else must approve diff --git a/src/drivers/wifi/generic/Makefile.inc b/src/drivers/wifi/generic/Makefile.inc index 5650d8a..91f22d1 100644 --- a/src/drivers/wifi/generic/Makefile.inc +++ b/src/drivers/wifi/generic/Makefile.inc @@ -1,6 +1,8 @@ ifeq ($(CONFIG_DRIVERS_WIFI_GENERIC),y) +romstage-y += generic.c + ramstage-y += generic.c ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c diff --git a/src/drivers/wifi/generic/chip.h b/src/drivers/wifi/generic/chip.h index 907b260..56a4afc 100644 --- a/src/drivers/wifi/generic/chip.h +++ b/src/drivers/wifi/generic/chip.h @@ -12,6 +12,13 @@ /* When set to true, this will add a _DSD which contains a single property, `DmaProperty`, set to 1, under the ACPI Device. */ bool is_untrusted; + + /* + * Applicable for Intel chipsets that use CNVi WiFi only. Set this to 1 + * to enable CNVi DDR RFIM (radio frequency interference mitigation); + * SoC code propagates this value the applicable FSP UPD. + */ + bool enable_cnvi_ddr_rfim; }; #endif /* _GENERIC_WIFI_H_ */ diff --git a/src/drivers/wifi/generic/generic.c b/src/drivers/wifi/generic/generic.c index de93741..a6936f1 100644 --- a/src/drivers/wifi/generic/generic.c +++ b/src/drivers/wifi/generic/generic.c @@ -7,6 +7,7 @@ #include <elog.h> #include "chip.h" #include "wifi_private.h" +#include "wifi.h" static void wifi_pci_dev_init(struct device *dev) { @@ -40,17 +41,39 @@ #endif }; +static bool is_cnvi(const struct device *dev) +{ +#if !DEVTREE_EARLY + return dev && dev->ops == &wifi_cnvi_ops; +#else + return dev && dev->path.type != DEVICE_PATH_PCI; +#endif +} + +bool wifi_generic_cnvi_ddr_rfim_enabled(const struct device *dev) +{ + const struct drivers_wifi_generic_config *config; + + if (!dev || !is_cnvi(dev) || !dev->chip_info) + return false; + + config = dev->chip_info; + return config->enable_cnvi_ddr_rfim; +} + static void wifi_generic_enable(struct device *dev) { - struct drivers_wifi_generic_config *config = dev ? dev->chip_info : NULL; + DEVTREE_CONST struct drivers_wifi_generic_config *config = dev ? dev->chip_info : NULL; if (!config) return; - if (dev->path.type == DEVICE_PATH_PCI) - dev->ops = &wifi_pcie_ops; - else +#if !DEVTREE_EARLY + if (is_cnvi(dev)) dev->ops = &wifi_cnvi_ops; + else + dev->ops = &wifi_pcie_ops; +#endif } struct chip_operations drivers_wifi_generic_ops = { diff --git a/src/drivers/wifi/generic/wifi.h b/src/drivers/wifi/generic/wifi.h new file mode 100644 index 0000000..54acfa4 --- /dev/null +++ b/src/drivers/wifi/generic/wifi.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> + +#ifndef _WIFI_GENERIC_WIFI_H_ +#define _WIFI_GENERIC_WIFI_H_ + +bool wifi_generic_cnvi_ddr_rfim_enabled(const struct device *dev); + +#endif /* _WIFI_GENERIC_WIFI_H_ */ diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 60d0469..f621b12 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -45,9 +45,6 @@ register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" - # Enable CNVi DDR RFIM - register "CnviDdrRfim" = "1" - # FIVR configurations for brya are disabled since the board doesn't have V1p05 and Vnn # bypass rails implemented. register "ext_fivr_settings" = "{ @@ -187,6 +184,7 @@ device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" + register "enable_cnvi_ddr_rfim" = "true" device generic 0 on end end end diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 6766406..7a16902 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -559,11 +559,6 @@ * 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16; see enum slew_rate for values */ uint8_t SlowSlewRate[NUM_VR_DOMAINS]; - - /* CNVi DDR RFIM Enable/Disable - * Default 0. Setting this to 1 enable CNVi DDR RFIM. - */ - bool CnviDdrRfim; }; typedef struct soc_intel_alderlake_config config_t; diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index e0f5eb7..3483abd 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -5,6 +5,7 @@ #include <cpu/x86/msr.h> #include <cpu/intel/cpu_ids.h> #include <device/device.h> +#include <drivers/wifi/generic/wifi.h> #include <fsp/util.h> #include <intelblocks/cpulib.h> #include <intelblocks/pcie_rp.h> @@ -208,7 +209,13 @@ m_cfg->GpioOverride = 0x1; /* CNVi DDR RFI Mitigation */ - m_cfg->CnviDdrRfim = config->CnviDdrRfim; + const struct device_path path[] = { + { .type = DEVICE_PATH_PCI, .pci.devfn = PCH_DEVFN_CNVI_WIFI }, + { .type = DEVICE_PATH_GENERIC, .generic.id = 0 } }; + const struct device *dev = find_dev_nested_path(pci_root_bus(), path, + ARRAY_SIZE(path)); + if (is_dev_enabled(dev)) + m_cfg->CnviDdrRfim = wifi_generic_cnvi_ddr_rfim_enabled(dev); } static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg, 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf9fba0a79d1f431269be5851b026ed966600160 Gerrit-Change-Number: 61638 Gerrit-PatchSet: 11 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Add companion device name to WWAN PCIe generic device
by Cliff Huang (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Bora Guvendik, Selma Bensaid. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62330 ) Change subject: mb/google/brya: Add companion device name to WWAN PCIe generic device ...................................................................... Patch Set 10: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62330/comment/b9847223_6829b3fe PS9, Line 14: BRANCH=firmware-brya-14505.Bre-brya-14505.B > `BRANCH=firmware-brya-14505. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia343c7545cf30bdbcd1de19e5eb84049dbb2977f Gerrit-Change-Number: 62330 Gerrit-PatchSet: 10 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Comment-Date: Wed, 09 Mar 2022 18:01:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add companion device name to WWAN PCIe generic device
by Tim Wawrzynczak (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Bora Guvendik, Cliff Huang, Selma Bensaid. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62330 ) Change subject: mb/google/brya: Add companion device name to WWAN PCIe generic device ...................................................................... Patch Set 10: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62330/comment/db63acff_a5087326 PS9, Line 14: BRANCH=firmware-brya-14505.Bre-brya-14505.B > `BRANCH=firmware-brya-14505. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia343c7545cf30bdbcd1de19e5eb84049dbb2977f Gerrit-Change-Number: 62330 Gerrit-PatchSet: 10 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Comment-Date: Wed, 09 Mar 2022 18:01:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add companion device name to WWAN PCIe generic device
by Cliff Huang (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Bora Guvendik, Cliff Huang, Selma Bensaid. Hello Bora Guvendik, build bot (Jenkins), Selma Bensaid, Tim Wawrzynczak, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62330 to look at the new patch set (#10). Change subject: mb/google/brya: Add companion device name to WWAN PCIe generic device ...................................................................... mb/google/brya: Add companion device name to WWAN PCIe generic device This is to merge PCIe ACPI code to WWAN device. Also, PCI and RTD3 devices are moved to overridetree.cb where WWAN is present. BUG=b:221250331 BRANCH=firmware-brya-14505.B TEST= Check that _DSD is added to WWAN device in SSDT for the variants. Check that RTD3 is added to WWAN device in SSDT for the variants. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Ia343c7545cf30bdbcd1de19e5eb84049dbb2977f --- M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/google/brya/variants/brya0/overridetree.cb M src/mainboard/google/brya/variants/brya4es/overridetree.cb M src/mainboard/google/brya/variants/redrix/overridetree.cb M src/mainboard/google/brya/variants/redrix4es/overridetree.cb 5 files changed, 104 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/62330/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/62330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia343c7545cf30bdbcd1de19e5eb84049dbb2977f Gerrit-Change-Number: 62330 Gerrit-PatchSet: 10 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/pcie/generic: Add support to generate code under companion de...
by Cliff Huang (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Bora Guvendik, Raul Rangel, Nico Huber, Selma Bensaid, Paul Menzel, Felix Held. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62301 ) Change subject: drivers/pcie/generic: Add support to generate code under companion device instead ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62301/comment/05770da9_d4cd5562 PS7, Line 34: BRANCH=firmware-brya-14505.Bre-brya-14505.B > `BRANCH=firmware-brya-14505. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80634bbfc2927f26f2a55a9c244eca517c437079 Gerrit-Change-Number: 62301 Gerrit-PatchSet: 8 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 09 Mar 2022 17:59:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/pcie/generic: Add support to generate code under companion de...
by Cliff Huang (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Bora Guvendik, Cliff Huang, Raul Rangel, Nico Huber, Selma Bensaid, Paul Menzel, Felix Held. Hello Bora Guvendik, build bot (Jenkins), Raul Rangel, Nico Huber, Selma Bensaid, Tim Wawrzynczak, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62301 to look at the new patch set (#8). Change subject: drivers/pcie/generic: Add support to generate code under companion device instead ...................................................................... drivers/pcie/generic: Add support to generate code under companion device instead Only one ACPI device should be added to a PCIe root port. For the root ports which already have device created, the generated code from this driver needs to be merged with the existing device. By default, this driver will create new device named DEV0. This change allows to generate code under an existing device. ex: (generate code under PXSX): Scope (\_SB.PCI0.RP01.PXSX) { Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") Package (0x01) { Package (0x02) { "UntrustedDevice", One } } }) } BUG=b:221250331 BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I80634bbfc2927f26f2a55a9c244eca517c437079 --- M src/drivers/pcie/generic/chip.h M src/drivers/pcie/generic/generic.c 2 files changed, 27 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/62301/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/62301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80634bbfc2927f26f2a55a9c244eca517c437079 Gerrit-Change-Number: 62301 Gerrit-PatchSet: 8 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/amd/chausie/devicetree: enable GFX HDA, ACP and XHCI2 devices
by Raul Rangel (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62571 ) Change subject: mb/amd/chausie/devicetree: enable GFX HDA, ACP and XHCI2 devices ...................................................................... Patch Set 1: (1 comment) File src/mainboard/amd/chausie/devicetree.cb: https://review.coreboot.org/c/coreboot/+/62571/comment/9e542aa6_fa2ac86e PS1, Line 80: xhci_2 Did you want to add an ACPI chip driver? ``` chip drivers/usb/acpi device ref usb2_port4 on end end ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/62571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I186797a832470eb17752e06aa2fcc0b5c9db0398 Gerrit-Change-Number: 62571 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 09 Mar 2022 17:22:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: prog_loader: Change legacy_romstage_select_and_load() to return cb_err
by Julius Werner (Code Review) 09 Mar '22

09 Mar '22

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62656 ) Change subject: prog_loader: Change legacy_romstage_select_and_load() to return cb_err ...................................................................... prog_loader: Change legacy_romstage_select_and_load() to return cb_err This is passing through a cb_err from cbfs_prog_stage_load(), so it should be declared to return that as well. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I5510d05953fe8c0e2cb511f01f862b66ced154ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/62656 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/x86/bootblock_normal.c M src/include/program_loading.h M src/lib/prog_loaders.c 3 files changed, 6 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/arch/x86/bootblock_normal.c b/src/arch/x86/bootblock_normal.c index 9341ac3..4bc9b01 100644 --- a/src/arch/x86/bootblock_normal.c +++ b/src/arch/x86/bootblock_normal.c @@ -12,7 +12,7 @@ return ++stagelist; } -int legacy_romstage_select_and_load(struct prog *romstage) +enum cb_err legacy_romstage_select_and_load(struct prog *romstage) { static const char *default_filenames = "normal/romstage\0fallback/romstage"; const char *boot_candidate; @@ -24,8 +24,8 @@ if (do_normal_boot()) { romstage->name = boot_candidate; - if (!cbfs_prog_stage_load(romstage)) - return 0; + if (cbfs_prog_stage_load(romstage) == CB_SUCCESS) + return CB_SUCCESS; } romstage->name = get_fallback(boot_candidate); diff --git a/src/include/program_loading.h b/src/include/program_loading.h index ba42465..7ff55fc 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -5,8 +5,7 @@ #include <bootmem.h> #include <commonlib/bsd/cbfs_serialized.h> #include <commonlib/region.h> -#include <stdint.h> -#include <stddef.h> +#include <types.h> enum { /* Last segment of program. Can be used to take different actions for @@ -139,7 +138,7 @@ void run_romstage(void); /* Runtime selector for CBFS_PREFIX of romstage. */ -int legacy_romstage_select_and_load(struct prog *romstage); +enum cb_err legacy_romstage_select_and_load(struct prog *romstage); /************************ * RAMSTAGE LOADING * diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index a296bd6..0e175c6 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -27,7 +27,7 @@ timestamp_add_now(TS_COPYROM_START); if (ENV_X86 && CONFIG(BOOTBLOCK_NORMAL)) { - if (legacy_romstage_select_and_load(&romstage)) + if (legacy_romstage_select_and_load(&romstage) != CB_SUCCESS) goto fail; } else { if (cbfs_prog_stage_load(&romstage)) -- To view, visit https://review.coreboot.org/c/coreboot/+/62656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5510d05953fe8c0e2cb511f01f862b66ced154ae Gerrit-Change-Number: 62656 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/kinox: Modify 15W SOC PL2/PL4 default setting
by Tim Wawrzynczak (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Dtrain Hsu, Nick Vaccaro, Zhuohao Lee. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62627 ) Change subject: mb/google/brya/var/kinox: Modify 15W SOC PL2/PL4 default setting ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: Thanks Felix, Dtrain you will need to rebase on master and update PCI_DEVICE_ID_ to PCI_DID_ -- To view, visit https://review.coreboot.org/c/coreboot/+/62627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2956705f7d26929c7cf2dd4e852fc61b619a83e5 Gerrit-Change-Number: 62627 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Wed, 09 Mar 2022 17:03:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/kinox: Modify 15W SOC PL2/PL4 default setting
by Felix Held (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Dtrain Hsu, Nick Vaccaro, Zhuohao Lee. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62627 ) Change subject: mb/google/brya/var/kinox: Modify 15W SOC PL2/PL4 default setting ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/kinox/ramstage.c: https://review.coreboot.org/c/coreboot/+/62627/comment/b8e6ab31_1028ec54 PS2, Line 13: PCI_DEVICE_ID_INTEL_ADL_P_ID_10 this patch needs to be updated since CB:39331 landed in the meantime -- To view, visit https://review.coreboot.org/c/coreboot/+/62627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2956705f7d26929c7cf2dd4e852fc61b619a83e5 Gerrit-Change-Number: 62627 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Wed, 09 Mar 2022 16:46:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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