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Change subject: soc/intel/common: Add IOE P2SB for TCSS
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Patchset:
PS2:
Can you use MTL_UPSTREAM as Topic?
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Change subject: mb/google/nissa/var/nivviks: Add GL9750 power sequence
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/brya/variants/nivviks/gpio.c:
https://review.coreboot.org/c/coreboot/+/62722/comment/3009e0d1_7164110b
PS1, Line 56: PAD_CFG_GPO(GPP_H12, 1, DEEP)
> I reference gimble CL. CB:60279 , but it can work in ramstage table as well, WDYT? I can remove it.
If it works in ramstage too, it seems simpler to just do it there. I think the only reason romstage tables were added in brya was to handle the WWAN power sequencing, which actually requires three different stages. If we can make do with only bootblock and ramstage for nissa, I think I'd prefer that.
Kangheui, do you have any thoughts?
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Change subject: mb/google/nissa/var/nivviks: Add GL9750 power sequence
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/brya/variants/nivviks/gpio.c:
https://review.coreboot.org/c/coreboot/+/62722/comment/a9b8b046_6b4b8cd9
PS1, Line 56: PAD_CFG_GPO(GPP_H12, 1, DEEP)
> Just curious, does it also work if you move this to ramstage? Are there any disadvantages to this? B […]
I reference gimble CL. CB:60279 , but it can work in ramstage table as well, WDYT? I can remove it.
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Change subject: mb/google/nissa/var/nivviks: Add GL9750 power sequence
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/nissa/var/nivviks: Add GL9750 power sequence
......................................................................
Patch Set 1:
(2 comments)
Patchset:
PS1:
Thanks Eric!
File src/mainboard/google/brya/variants/nivviks/gpio.c:
https://review.coreboot.org/c/coreboot/+/62722/comment/3507f3d9_2976d22b
PS1, Line 56: PAD_CFG_GPO(GPP_H12, 1, DEEP)
Just curious, does it also work if you move this to ramstage? Are there any disadvantages to this? Because it would avoid the need to add a romstage table.
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Change subject: mb/google/nissa/var/nivviks: Enable pen garage
......................................................................
Patch Set 2: Code-Review+2
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Hello build bot (Jenkins), Cliff Huang, Selma Bensaid, Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62654
to look at the new patch set (#9).
Change subject: soc/intel/alderlake: Add EPP override support
......................................................................
soc/intel/alderlake: Add EPP override support
This updates energy performance preference value to all logical CPUs
when the corresponding chip config is true.
BUG=b:219785001
BRANCH=firmware-brya-14505.B
Signed-off-by: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com>
Change-Id: Ie59623fe715b0c545f8d4b6c22ab2ce670a29798
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/cpu.c
2 files changed, 23 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/62654/9
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Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62627 )
Change subject: mb/google/brya/var/kinox: Modify 15W SOC PL2/PL4 default setting
......................................................................
Patch Set 4:
(2 comments)
Patchset:
PS2:
> Thanks Felix, Dtrain you will need to rebase on master and update PCI_DEVICE_ID_ to PCI_DID_
Done
File src/mainboard/google/brya/variants/kinox/ramstage.c:
https://review.coreboot.org/c/coreboot/+/62627/comment/2c6e3fe2_c21578fb
PS2, Line 13: PCI_DEVICE_ID_INTEL_ADL_P_ID_10
> this patch needs to be updated since CB:39331 landed in the meantime
Thanks Felix for review. Rebase and update naming.
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