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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya/var/kinox: update overridetree
......................................................................
mb/google/brya/var/kinox: update overridetree
1. Update override devicetree based on schematics.
2. ALC5682I-VS is for audio codec.
BUG=b:218786363, b:214025396, b:212183045
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com>
Change-Id: I08a1c2f784175b208ccdc562668041f432618dfc
---
M src/mainboard/google/brya/variants/kinox/overridetree.cb
1 file changed, 212 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/62553/11
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Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Zhuohao Lee,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62553
to look at the new patch set (#10).
Change subject: mb/google/brya/var/kinox: update overridetree
......................................................................
mb/google/brya/var/kinox: update overridetree
1. Update override devicetree based on schematics.
2. ALC5682I-VS is for audio codec.
BUG=b:218786363, b:214025396, b:212183045
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com>
Change-Id: I08a1c2f784175b208ccdc562668041f432618dfc
---
M src/mainboard/google/brya/variants/kinox/overridetree.cb
1 file changed, 212 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/62553/10
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Curtis Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62727 )
Change subject: soc/intel/alderlake: Update ADL-P id list of th VccIn Aux Imon IccMax values
......................................................................
soc/intel/alderlake: Update ADL-P id list of th VccIn Aux Imon IccMax values
Add ADL-P MCH ID 4, 8, 9, 10 into this list.
BUG=b:222038287
TEST=Build and check fsp log to confirm the settings are set properly.
Signed-off-by: Curtis Chen <curtis.chen(a)intel.com>
Change-Id: I2cee31ba56e0b142c50a745c453968635e86296e
---
M src/soc/intel/alderlake/fsp_params.c
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/62727/1
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index b4e833b..9833b3d 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -311,9 +311,13 @@
switch (mch_id) {
case PCI_DID_INTEL_ADL_P_ID_1:
case PCI_DID_INTEL_ADL_P_ID_3:
+ case PCI_DID_INTEL_ADL_P_ID_4:
case PCI_DID_INTEL_ADL_P_ID_5:
case PCI_DID_INTEL_ADL_P_ID_6:
case PCI_DID_INTEL_ADL_P_ID_7:
+ case PCI_DID_INTEL_ADL_P_ID_8:
+ case PCI_DID_INTEL_ADL_P_ID_9:
+ case PCI_DID_INTEL_ADL_P_ID_10:
tdp = get_cpu_tdp();
if (tdp == TDP_45W)
return ICC_MAX_TDP_45W;
--
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Hello build bot (Jenkins), Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
Change subject: mb/google/brya/var/primus{4es}: add eMMC enable pin in ramstage
......................................................................
mb/google/brya/var/primus{4es}: add eMMC enable pin in ramstage
Program the BayHub eMMC enable pin in ram stage to prevent baseboard
override the setting leads RTD3 not able to control when enter and
exit suspend state.
BUG=b:222436260
TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage
scope enable pin while performing suspend stress and enable pin
works as expected.
test suspend stress 1000 cycles passed on primus.
Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com>
Change-Id: I1b6f164cc326bd368addb1e143ad2cbd449bb08d
---
M src/mainboard/google/brya/variants/primus/gpio.c
M src/mainboard/google/brya/variants/primus4es/gpio.c
2 files changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/62703/5
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Attention is currently required from: Casper Chang.
Hello build bot (Jenkins), Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62703
to look at the new patch set (#4).
Change subject: mb/google/brya/var/primus{4es}: add eMMC enable pin in ramstage
......................................................................
mb/google/brya/var/primus{4es}: add eMMC enable pin in ramstage
Program the BayHub eMMC enable pin in ram stage to prevent baseboad
override the setting leads RTD3 not able to control when enter and
exit suspend state.
BUG=b:222436260
TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage
scope enable pin while performing suspend stress and enable pin
works as expected.
test suspend stress 1000 cycles passed on primus.
Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com>
Change-Id: I1b6f164cc326bd368addb1e143ad2cbd449bb08d
---
M src/mainboard/google/brya/variants/primus/gpio.c
M src/mainboard/google/brya/variants/primus4es/gpio.c
2 files changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/62703/4
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Attention is currently required from: Douglas Anderson, Paul Menzel, Bob Moragues, Julius Werner.
Mars Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62642 )
Change subject: mb/google/trogdor: Add variant Gelarshie
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/trogdor/Kconfig:
https://review.coreboot.org/c/coreboot/+/62642/comment/9a202610_44ba87ba
PS3, Line 26: default y if BOARD_GOOGLE_COACHZ
> If you're similar to coachz, should you set HAS_FINGERPRINT ?
There is no fingerprint component on Gelarshie.
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Frank Chu has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/62704 )
Change subject: mb/google/dedede/var/galtic: update Wifi SAR for for galnat
......................................................................
mb/google/dedede/var/galtic: update Wifi SAR for for galnat
Add wifi sar for galnat/galnat360
Using convertible mode of SKU ID to load wifi table.
Each Project and SKU ID correspond as below
galtic (sku id:0x120000)
galith (sku id:0x130000)
galnat (sku id:0x140000)*
gallop (sku id:0x150000)
galtic360 (sku id:0x260000)
galith360 (sku id:0x270000)
galnat360 (sku id:0x2B0000)*
BUG=b:222008376
TEST=emerge-dedede coreboot chromeos-bootimage \
coreboot-private-files-baseboard-dedede
verify the SAR table is correct in each project
Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com>
Change-Id: I868a7416a002732736cabea48ce80548ea75e517
---
M src/mainboard/google/dedede/variants/galtic/variant.c
1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/62704/3
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Frank Chu has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/62704 )
Change subject: mb/google/dedede/var/galtic: update Wifi SAR for for galnat Add wifi sar for galnat/galnat360 Using convertible mode of SKU ID to load wifi table.
......................................................................
mb/google/dedede/var/galtic: update Wifi SAR for for galnat
Add wifi sar for galnat/galnat360
Using convertible mode of SKU ID to load wifi table.
Each Project and SKU ID correspond as below
galtic (sku id:0x120000)
galith (sku id:0x130000)
galnat (sku id:0x140000)*
gallop (sku id:0x150000)
galtic360 (sku id:0x260000)
galith360 (sku id:0x270000)
galnat360 (sku id:0x2B0000)*
BUG=b:222008376
TEST=emerge-dedede coreboot chromeos-bootimage \
coreboot-private-files-baseboard-dedede
verify the SAR table is correct in each project
Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com>
Change-Id: I868a7416a002732736cabea48ce80548ea75e517
---
M src/mainboard/google/dedede/variants/galtic/variant.c
1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/62704/2
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