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Change subject: soc/intel/common/block/cpu: Enable ROM caching in ramstage
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62838/comment/1ff3231c_beb42056
PS1, Line 9: This patch ensures to have `BIOS region` and `extended BIOS` region is
: cached if the boot device is memory mapped
Maybe:
> Cache the BIOS region and extendend BIOS region if the boot device is memory mapped, which …
https://review.coreboot.org/c/coreboot/+/62838/comment/0e6e087d_ee440c12
PS1, Line 9: This patch ensures to have `BIOS region` and `extended BIOS` region is
: cached if the boot device is memory mapped, which is mostly the case
: with Intel SoC platform.
Why should this be done? Lower boot time?
https://review.coreboot.org/c/coreboot/+/62838/comment/2ae1a277_0cda4883
PS1, Line 12:
Tested on what device?
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Change subject: soc/intel/common/fast_spi: support caching `ext_bios` in ramstage
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62837/comment/6719842a_2c64070b
PS2, Line 9: This patch provides a way to cache ext_bios region for all stages.
Why is that caching useful?
https://review.coreboot.org/c/coreboot/+/62837/comment/6b99dbbf_caeec474
PS2, Line 11: TEST=Able to see ext_bios region in MTRR snapshot when cached.
On what board? Any timing differences?
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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62793 )
Change subject: cpu/x86/smm: Add smm_get_cbmemc_buffer for legacy SMI handler
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> I'd prefer not linking this code at buildtime instead of adding runtime failures.
We can tackle that one of two ways:
1) We can add `&& !CONFIG(LEGACY_SMP_INIT)` into [cbmem-console.c](https://source.chromium.org/chromiumos/chromiumos/codesear…
2) We can add the same condition to https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi…
Both I would argue are a bit ugly. `LEGACY_SMP_INIT` is scheduled to be deleted. I would like to avoid adding `LEGACY_SMP_INIT` checks just to have someone clean them up later. Thoughts?
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Change subject: mb/google/nissa/var/nivviks: Add TcssAuxori for nivviks
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/brya/variants/nivviks/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/62731/comment/86220e25_6e1ec766
PS2, Line 12: register "TcssAuxOri" = "5"
What does 5 mean? Please extend the commit message.
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Change subject: mb/google/nissa/var/nivviks: Add TcssAuxori for nivviks
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Patch Set 2: Code-Review+1
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Change subject: soc/intel/common/fast_spi: support caching `ext_bios` in ramstage
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62837/comment/c5b0ada4_53897b8a
PS1, Line 9: stage
> stages
Ack
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Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Eric Lai, Werner Zeh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62837
to look at the new patch set (#2).
Change subject: soc/intel/common/fast_spi: support caching `ext_bios` in ramstage
......................................................................
soc/intel/common/fast_spi: support caching `ext_bios` in ramstage
This patch provides a way to cache ext_bios region for all stages.
TEST=Able to see ext_bios region in MTRR snapshot when cached.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I87139a9ed7eb9ed43164a5199aa436dd1219145c
---
M src/soc/intel/common/block/fast_spi/fast_spi.c
1 file changed, 8 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/62837/2
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Change subject: intel/block/cpu: Provide a way to cache the flash region temporary
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Abandoned
Fixed in CB:62838
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Change subject: soc/intel/elkhartlake: Enable SPI flash caching before payload is loaded
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