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Change subject: mb/google/brya/var/kinox: Modify the DPTF/Fan parameters
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Patch Set 6: Code-Review+2
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Change subject: soc/intel/common/block/cpu: Enable ROM caching in ramstage
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS1:
> Works for me, payload loading is faster now. Thanks Subrata.
Thanks Werner, I have borrowed your commit msg boot time improvement numbers.
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Change subject: soc/intel/common/block/cpu: Enable ROM caching in ramstage
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62838/comment/7172e466_aa7d1ad3
PS1, Line 9: This patch ensures to have `BIOS region` and `extended BIOS` region is
: cached if the boot device is memory mapped
> Maybe: […]
Ack
https://review.coreboot.org/c/coreboot/+/62838/comment/c7a6f335_c4ac9e51
PS1, Line 9: This patch ensures to have `BIOS region` and `extended BIOS` region is
: cached if the boot device is memory mapped, which is mostly the case
: with Intel SoC platform.
> Why should this be done? Lower boot time?
Ack
https://review.coreboot.org/c/coreboot/+/62838/comment/2a16ec4a_982a2753
PS1, Line 12:
> Tested on what device?
Ack
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Subrata Banik has uploaded a new patch set (#2) to the change originally created by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/62838 )
Change subject: soc/intel/common/block/cpu: Enable ROM caching in ramstage
......................................................................
soc/intel/common/block/cpu: Enable ROM caching in ramstage
Cache the BIOS region and extended BIOS region if the boot device is
memory mapped, which is mostly the case with Intel SoC platform.
Having the ROM region cached helped to improve the pre-boot time.
TEST=Able to boot redrix to Chrome OS without seeing any sluggishness.
Additionally verified on EHL board (from siemens), shows significant
savings in payload loading time as below:
Here is the timestamp snippet showing the payload load time as a
comparison between current upstream and the patched version:
upstream:
90:starting to load payload 1,072,459 (1,802)
958:calling FspNotify(ReadyToBoot) 12,818,079 (11,745,619)
with this patch:
90:starting to load payload 1,072,663 (2,627)
958:calling FspNotify(ReadyToBoot) 5,299,535 (4,226,871)
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I02b80eefbb3b19331698a205251a0c4d17be534c
---
M src/soc/intel/common/block/cpu/mp_init.c
1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/62838/2
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Change subject: soc/intel/common/fast_spi: support caching `ext_bios` in ramstage
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62837/comment/e7b852a3_5568b5a6
PS2, Line 9: This patch provides a way to cache ext_bios region for all stages.
> Why is that caching useful?
Ack
https://review.coreboot.org/c/coreboot/+/62837/comment/6a719ad2_b13e8446
PS2, Line 11: TEST=Able to see ext_bios region in MTRR snapshot when cached.
> On what board? Any timing differences?
Ack
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Subrata Banik has uploaded a new patch set (#3) to the change originally created by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/62837 )
Change subject: soc/intel/common/fast_spi: support caching `ext_bios` in ramstage
......................................................................
soc/intel/common/fast_spi: support caching `ext_bios` in ramstage
This patch provides a way to cache `ext_bios` region for all stages to
save boot time.
TEST=Able to see the ext_bios region in MTRR snapshot when cached on
the Brya variants.
Here is the timestamp snippet showing the payload load time as a
comparison between current upstream and the patched version:
upstream:
90:starting to load payload 1,072,459 (1,802)
958:calling FspNotify(ReadyToBoot) 12,818,079 (11,745,619)
with this patch:
90:starting to load payload 1,072,663 (2,627)
958:calling FspNotify(ReadyToBoot) 5,299,535 (4,226,871)
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I87139a9ed7eb9ed43164a5199aa436dd1219145c
---
M src/soc/intel/common/block/fast_spi/fast_spi.c
1 file changed, 8 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/62837/3
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Change subject: soc/intel/common: Retry MEI CSE DISABLE command
......................................................................
Patch Set 7: Code-Review+2
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Change subject: soc/intel/common: Retry END_OF_POST command
......................................................................
Patch Set 13: Code-Review+2
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Change subject: 3rdparty/amd_blobs: advance submodule pointer
......................................................................
Patch Set 1: Code-Review+2
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Change subject: x86/smbios_defaults: Set default system manufacturer for ChromeOS devices
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
File src/arch/x86/smbios_defaults.c:
https://review.coreboot.org/c/coreboot/+/62796/comment/3e2e5919_a6c23cbd
PS1, Line 121: return smbios_mainboard_manufacturer();
> I'm unclear what exactly you're looking for here
When no log message is needed, I meant:
return CONFIG(MAINBOARD_HAS_CHROMEOS) ? "Google" : smbios_mainboard_manufacturer();
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