coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: Documentation: Add RFC how to handle UEFI variables
by Angel Pons (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62015 ) Change subject: Documentation: Add RFC how to handle UEFI variables ...................................................................... Patch Set 5: (3 comments) File Documentation/RFC/efivars.md: https://review.coreboot.org/c/coreboot/+/62015/comment/206dbfd7_43010edf PS5, Line 7: d remove `d` Also applies to related words https://review.coreboot.org/c/coreboot/+/62015/comment/93b765f2_b62e06fd PS5, Line 12: priviledged remove spurious `d` https://review.coreboot.org/c/coreboot/+/62015/comment/a6b1202f_75f57e9c PS5, Line 24: priviledges remove spurious `d` -- To view, visit https://review.coreboot.org/c/coreboot/+/62015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddf43a9ff6bf25232fbe2aa8aae2e466e5514492 Gerrit-Change-Number: 62015 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Tue, 15 Mar 2022 14:08:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: option: Allow to use the EFI variable driver as option backend
by Angel Pons (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Sean Rhodes, Michał Żygowski, Patrick Rudolph, Matt DeVillier. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62562 ) Change subject: option: Allow to use the EFI variable driver as option backend ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I520eca96bcd573f825ed35a29bf8f750e313a02d Gerrit-Change-Number: 62562 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Tue, 15 Mar 2022 14:06:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/efi: Add EFI variable store option support
by Angel Pons (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Sean Rhodes, Martin Roth, Patrick Rudolph, Jakub Czapiga, Matt DeVillier, Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52564 ) Change subject: drivers/efi: Add EFI variable store option support ...................................................................... Patch Set 10: (16 comments) File src/drivers/efi/Kconfig: https://review.coreboot.org/c/coreboot/+/52564/comment/e297b055_0fd7a171 PS10, Line 1: DRIVERS_EFI_VARIABLE_STORE > Should it select the right UDK to get the UEFI headers? If it only needs the headers, why not include them directly? I'd avoid binding to a specific edk2 version if possible. https://review.coreboot.org/c/coreboot/+/52564/comment/d798a79c_b4826078 PS10, Line 4: Adds a driver that is able to read and write an EFI formated > 'formated' may be misspelled - perhaps 'formatted'? Please fix. File src/drivers/efi/efivars.c: https://review.coreboot.org/c/coreboot/+/52564/comment/f883c618_858dbcb7 PS10, Line 75: WA ? https://review.coreboot.org/c/coreboot/+/52564/comment/1f84da77_92a2bbc5 PS10, Line 83: while (1) I'd prefer a for-loop to avoid going past the end of `msg` https://review.coreboot.org/c/coreboot/+/52564/comment/6db235dc_f21391ff PS10, Line 86: (r = (c - msg[i])) Is it necessary to do this assignment in the condition? https://review.coreboot.org/c/coreboot/+/52564/comment/ae722f5f_e17a9dd5 PS10, Line 90: ; not needed https://review.coreboot.org/c/coreboot/+/52564/comment/101f768c_742b45a5 PS10, Line 110: ; Not needed https://review.coreboot.org/c/coreboot/+/52564/comment/41ee1f5a_8f53a2b7 PS10, Line 119: ; Not needed https://review.coreboot.org/c/coreboot/+/52564/comment/983b11a5_9e30288a PS10, Line 208: zd zu https://review.coreboot.org/c/coreboot/+/52564/comment/11929953_f52d7fa4 PS10, Line 271: void * Why is this a void pointer? https://review.coreboot.org/c/coreboot/+/52564/comment/9931f163_12abb90b PS10, Line 443: args.guid = guid; : args.name = name; : args.size = size; : args.data = dest; Why not initialise the struct directly, instead of assigning each member individually? https://review.coreboot.org/c/coreboot/+/52564/comment/3b0b533c_9129f88e PS10, Line 532: (hdr.StartId != UINT16_MAX || : hdr.State != UINT8_MAX || : hdr.DataSize != UINT32_MAX || : hdr.NameSize != UINT32_MAX || : hdr.Attributes != UINT32_MAX) Why not use `memcmp()` instead? File tests/drivers/efivars.c: https://review.coreboot.org/c/coreboot/+/52564/comment/b782cc30_5d13ca8f PS10, Line 10: uint8_t #include <types.h> https://review.coreboot.org/c/coreboot/+/52564/comment/32085437_cc73d047 PS10, Line 116: + nit: spaces around `+` https://review.coreboot.org/c/coreboot/+/52564/comment/f4972734_b89bf296 PS10, Line 119: 89 What does this magic 89 number mean? https://review.coreboot.org/c/coreboot/+/52564/comment/b3345253_730605ca PS10, Line 119: + nit: spaces around `+` -- To view, visit https://review.coreboot.org/c/coreboot/+/52564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8079f71d29da5dc2db956fc68bef1486fe3906bb Gerrit-Change-Number: 52564 Gerrit-PatchSet: 10 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Patrick Rudolph Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 15 Mar 2022 14:04:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code
by build bot (Jenkins) (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Jeff Daly, Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Michael Niewöhner, Andrey Petrov, Patrick Rudolph, Nico Huber, Anjaneya "Reddy" Chagam, Johnny Lin, Tim Wawrzynczak, Suresh Bellampalli, Christian Walter, Vanessa Eusebio, Lean Sheng Tan, Michal Motyl, Werner Zeh, Tim Chu. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62064 ) Change subject: soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code ...................................................................... Patch Set 11: (6 comments) File src/soc/intel/common/block/pmc/pmclib.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144011): https://review.coreboot.org/c/coreboot/+/62064/comment/24c7dacb_9417f4f5 PS11, Line 632: if (CONFIG(SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE) && (GEN_PMCON_A <= 0xff)) suspect code indent for conditional statements (8, 8) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144011): https://review.coreboot.org/c/coreboot/+/62064/comment/d7b9067b_8fe4665f PS11, Line 633: pmc_clear_pmcon_sts_pci(); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144011): https://review.coreboot.org/c/coreboot/+/62064/comment/6fe1ab74_a1183211 PS11, Line 633: pmc_clear_pmcon_sts_pci(); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144011): https://review.coreboot.org/c/coreboot/+/62064/comment/468c0c1b_c60f9328 PS11, Line 634: else suspect code indent for conditional statements (8, 8) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144011): https://review.coreboot.org/c/coreboot/+/62064/comment/c87a78b8_1955bfca PS11, Line 635: pmc_clear_pmcon_sts_mmio(); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144011): https://review.coreboot.org/c/coreboot/+/62064/comment/c7ed3b3e_6430ce92 PS11, Line 635: pmc_clear_pmcon_sts_mmio(); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/62064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1 Gerrit-Change-Number: 62064 Gerrit-PatchSet: 11 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 15 Mar 2022 14:02:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code
by Subrata Banik (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Jeff Daly, Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Michael Niewöhner, Andrey Petrov, Patrick Rudolph, Nico Huber, Anjaneya "Reddy" Chagam, Johnny Lin, Tim Wawrzynczak, Suresh Bellampalli, Christian Walter, Vanessa Eusebio, Lean Sheng Tan, Michal Motyl, Werner Zeh, Tim Chu. Hello build bot (Jenkins), Jeff Daly, Mariusz Szafrański, Jonathan Zhang, Angel Pons, Arthur Heymans, Michael Niewöhner, Andrey Petrov, Patrick Rudolph, Anjaneya "Reddy" Chagam, Johnny Lin, Christian Walter, Suresh Bellampalli, Tim Wawrzynczak, Vanessa Eusebio, Nick Vaccaro, siemens-bot, Lean Sheng Tan, Michal Motyl, Werner Zeh, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62064 to look at the new patch set (#11). Change subject: soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code ...................................................................... soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code This patch moves `pmc_clear_pmcon_sts` function into common code and remove SoC specific instances. Accessing PMC GEN_PMCON_A register differs between different Intel chipsets. Typically, there are two possible ways to perform GEN_PMCON_A register programming (like `pmc_clear_pmcon_sts()`) as: 1. Using PCI configuration space when GEN_PMCON_A is a PCI configuration register. And, the PMC device is visible over the PCI bus, so the SoC user selects `SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE` Kconfig. 2. Using MMIO access when GEN_PMCON_A is a memory mapped register. And, the PMC device is not visible over the PCI bus and hidden by the FSP. Unfortunately, there is a 3rd case as well with Apollolake platform where SoC selects SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE Kconfig and GEN_PMCON_A is memory mapped, and this scenario can't be fit into either of the two cases above, unless provided with one more check to identify if GEN_PMCON_A is a PCI configuration space register (offset within 256 bytes) or memory mapped. Hence, added a check along with SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE Kconfig to see if the register (i.e., GEN_PMCON_A) actually belongs to the PCI config space. BUG=b:211954778 TEST=Able to build brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1 --- M src/soc/intel/alderlake/include/soc/pm.h M src/soc/intel/alderlake/pmutil.c M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/cannonlake/include/soc/pm.h M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/denverton_ns/include/soc/pm.h M src/soc/intel/denverton_ns/pmutil.c M src/soc/intel/elkhartlake/include/soc/pm.h M src/soc/intel/elkhartlake/pmutil.c M src/soc/intel/icelake/include/soc/pm.h M src/soc/intel/icelake/pmutil.c M src/soc/intel/jasperlake/include/soc/pm.h M src/soc/intel/jasperlake/pmutil.c M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/pmutil.c M src/soc/intel/tigerlake/include/soc/pm.h M src/soc/intel/tigerlake/pmutil.c M src/soc/intel/xeon_sp/include/soc/pm.h M src/soc/intel/xeon_sp/pmutil.c 23 files changed, 60 insertions(+), 173 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/62064/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/62064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1 Gerrit-Change-Number: 62064 Gerrit-PatchSet: 11 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/cpu: Enable ROM caching in ramstage
by Subrata Banik (Code Review) 15 Mar '22

15 Mar '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62838 ) Change subject: soc/intel/common/block/cpu: Enable ROM caching in ramstage ...................................................................... soc/intel/common/block/cpu: Enable ROM caching in ramstage This patch ensures to have `BIOS region` and `extended BIOS` region is cached if the boot device is memory mapped, which is mostly the case with Intel SoC platform. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I02b80eefbb3b19331698a205251a0c4d17be534c --- M src/soc/intel/common/block/cpu/mp_init.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/62838/1 diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 99d9507..2d838c5 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -152,6 +152,14 @@ init_cpus(); } +static void post_cpus_add_romcache(void) +{ + if (!CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) + return; + + fast_spi_cache_bios_region(); +} + static void wrapper_x86_setup_mtrrs(void *unused) { x86_setup_mtrrs_with_detect(); @@ -163,6 +171,7 @@ if (mp_run_on_all_cpus(&wrapper_x86_setup_mtrrs, NULL) != CB_SUCCESS) printk(BIOS_ERR, "MTRR programming failure\n"); + post_cpus_add_romcache(); x86_mtrr_check(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/62838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02b80eefbb3b19331698a205251a0c4d17be534c Gerrit-Change-Number: 62838 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/fast_spi: support caching `ext_bios` in ramstage
by Subrata Banik (Code Review) 15 Mar '22

15 Mar '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62837 ) Change subject: soc/intel/common/fast_spi: support caching `ext_bios` in ramstage ...................................................................... soc/intel/common/fast_spi: support caching `ext_bios` in ramstage This patch provides a way to cache ext_bios region for all stage. TEST=Able to see ext_bios region in MTRR snapshot when cached. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I87139a9ed7eb9ed43164a5199aa436dd1219145c --- M src/soc/intel/common/block/fast_spi/fast_spi.c 1 file changed, 8 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/62837/1 diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 0e01231..7be71a2 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -245,10 +245,14 @@ if (!fast_spi_ext_bios_cache_range(&ext_bios_base, &ext_bios_size)) return; - int mtrr = get_free_var_mtrr(); - if (mtrr == -1) - return; - set_var_mtrr(mtrr, ext_bios_base, ext_bios_size, type); + if (ENV_PAYLOAD_LOADER) { + mtrr_use_temp_range(ext_bios_base, ext_bios_size, type); + } else { + int mtrr = get_free_var_mtrr(); + if (mtrr == -1) + return; + set_var_mtrr(mtrr, ext_bios_base, ext_bios_size, type); + } } void fast_spi_cache_ext_bios_postcar(struct postcar_frame *pcf) -- To view, visit https://review.coreboot.org/c/coreboot/+/62837 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87139a9ed7eb9ed43164a5199aa436dd1219145c Gerrit-Change-Number: 62837 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/apollolake: Create components required for IFWI stitching
by Arthur Heymans (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Sean Rhodes, Nico Huber, Martin Roth, Andrey Petrov, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61872 ) Change subject: soc/apollolake: Create components required for IFWI stitching ...................................................................... Patch Set 14: (1 comment) File Makefile.inc: https://review.coreboot.org/c/coreboot/+/61872/comment/1510d8d3_26897c7d PS14, Line 1311: # IFWI Stitching Can this SOC specific code be moved out of the main makefile.inc? -- To view, visit https://review.coreboot.org/c/coreboot/+/61872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a64e602b8e0d53e1a51b2fbce583c40dfb68c79 Gerrit-Change-Number: 61872 Gerrit-PatchSet: 14 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 15 Mar 2022 13:57:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/apollolake: Create components required for IFWI stitching
by Arthur Heymans (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Sean Rhodes, Nico Huber, Martin Roth, Andrey Petrov, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61872 ) Change subject: soc/apollolake: Create components required for IFWI stitching ...................................................................... Patch Set 14: (1 comment) File Makefile.inc: https://review.coreboot.org/c/coreboot/+/61872/comment/47112120_c217eba7 PS14, Line 1321: $(objcbfs)/ibbm.rom: : # Size is calculate as: : # IBBP-Sub-Partition - IBBL - Manifest - BPM.met - Padding : python -c "import struct; fp = open ('$@', 'wb'); \ : fp.write (b'\xFF' * \ : $(shell echo $$((32768 - \ : $(shell stat -Lc %s $(objcbfs)/ibbl.rom) \ : - 748 - 180 - 3168)))); fp.close();" : printf "\nBuilt $@ (0x%x)\n" `stat -c "%s" $@` Does this need a dependency? Also inline python inside makefiles is a bad idea. "dd if=/dev/zero bs=1 count=#filesize | tr "\000" "\377" > foo" could achieve the same? -- To view, visit https://review.coreboot.org/c/coreboot/+/61872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a64e602b8e0d53e1a51b2fbce583c40dfb68c79 Gerrit-Change-Number: 61872 Gerrit-PatchSet: 14 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 15 Mar 2022 13:56:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/smmstore: Expose region device
by Angel Pons (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62014 ) Change subject: drivers/smmstore: Expose region device ...................................................................... Patch Set 3: Code-Review+1 (1 comment) File src/drivers/smmstore/store.c: https://review.coreboot.org/c/coreboot/+/62014/comment/9997efef_750da590 PS3, Line 96: else Coding style says that the else branch should have braces. https://doc.coreboot.org/contributing/coding_style.html#placing-braces-and-… -- To view, visit https://review.coreboot.org/c/coreboot/+/62014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6316b703829590bd6f41c3d4013b4a4660b9cbab Gerrit-Change-Number: 62014 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Tue, 15 Mar 2022 13:46:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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