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Change subject: soc/intel/common/fast_spi: support caching `ext_bios` in ramstage
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62837/comment/f80e5da3_dca4c5bb
PS1, Line 9: stage
stages
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Change subject: soc/intel/common/block/cpu: Enable ROM caching in ramstage
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
Works for me, payload loading is faster now. Thanks Subrata.
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Change subject: x86/smbios_defaults: Set default system manufacturer for ChromeOS devices
......................................................................
Patch Set 2:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62796/comment/4b7411c2_a7970602
PS1, Line 9: Currently, many Linux drivers use DMI quirks to identify ChromeOS devices and
: handle them accordingly: namely they look for the SMBIOS system manufactuer
: to be "GOOGLE" or "Google", and the bios-vendor to be coreboot. Historically
: this was consistently the case, but recent model ChromeOS devices allow the
: OEM to set the mainboard manufacturer, which is also the default system
: manufacturer. This breaks many DMI quirks, notably ones used by SOF (sound
: open firmware) for audio.
> Please reflow for 72 characters per line.
Done
https://review.coreboot.org/c/coreboot/+/62796/comment/5479c639_20835a6e
PS1, Line 14: This breaks many DMI quirks, notably ones used by SOF (sound
: open firmware) for audio.
> Do you know of the Chromium OS Linux kernel commit making this work for Chromium OS?
there is none, as the SoF code backported to the ChromeOS kernel doesn't rely on DMI quirks
File src/arch/x86/smbios_defaults.c:
https://review.coreboot.org/c/coreboot/+/62796/comment/2e27ef46_4eb8e4d3
PS1, Line 119: return "Google";
> I would like to avoid vendor specific configurations in common code. […]
I think that will work, will give it a look
https://review.coreboot.org/c/coreboot/+/62796/comment/ae45f9ff_e721dbe3
PS1, Line 121: return smbios_mainboard_manufacturer();
> You could you the ternary operator, use the if statement, and also add a log message, that it’s over […]
I'm unclear what exactly you're looking for here
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Change subject: include/efi: Clean up efi_datatype.h file
......................................................................
Patch Set 2: Code-Review+1
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I'd like you to reexamine a change. Please visit
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Change subject: x86/smbios_defaults: Set default system manufacturer for ChromeOS devices
......................................................................
x86/smbios_defaults: Set default system manufacturer for ChromeOS devices
Currently, many Linux drivers use DMI quirks to identify ChromeOS
devices and handle them accordingly: namely they look for the SMBIOS
system manufactuer to be "GOOGLE" or "Google", and the bios-vendor to be
coreboot. Historically this was consistently the case, but recent model
ChromeOS devices allow the OEM to set the mainboard manufacturer, which
is also the default system manufacturer. This breaks many DMI quirks,
notably ones used by SOF (sound open firmware) for audio.
To fix this, set the default system manufactuer for ChromeOS devices to
"Google" conditional on CONFIG_MAINBOARD_HAS_CHROMEOS, leaving the OEM
customization in place for the mainboard manufacturer.
Test: build/boot google/bloog with Linux 5.16, verify SOF drivers
correctly detect device as a Chromebook and load the appropriate
audio firmware.
Change-Id: I9de17fa12689ab4e627b995818aa3d2653102b04
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/arch/x86/smbios_defaults.c
1 file changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/62796/2
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Change subject: soc/intel/common/block/cpu: Enable ROM caching in ramstage
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
It looks like this is already done on the APL platform
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Change subject: soc/intel/common/fast_spi: support caching `ext_bios` in ramstage
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/apollolake: Create components required for IFWI stitching
......................................................................
Patch Set 16:
(2 comments)
File Makefile.inc:
https://review.coreboot.org/c/coreboot/+/61872/comment/4135ab4f_8ee221b3
PS14, Line 1311: # IFWI Stitching
> Can this SOC specific code be moved out of the main makefile. […]
Done
https://review.coreboot.org/c/coreboot/+/61872/comment/04a589e7_3f1dec41
PS14, Line 1321: $(objcbfs)/ibbm.rom:
: # Size is calculate as:
: # IBBP-Sub-Partition - IBBL - Manifest - BPM.met - Padding
: python -c "import struct; fp = open ('$@', 'wb'); \
: fp.write (b'\xFF' * \
: $(shell echo $$((32768 - \
: $(shell stat -Lc %s $(objcbfs)/ibbl.rom) \
: - 748 - 180 - 3168)))); fp.close();"
: printf "\nBuilt $@ (0x%x)\n" `stat -c "%s" $@`
> Does this need a dependency? Also inline python inside makefiles is a bad idea. […]
I did not know dd could do that, magic!
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Change subject: soc/apollolake: Create components required for IFWI stitching
......................................................................
soc/apollolake: Create components required for IFWI stitching
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I2a64e602b8e0d53e1a51b2fbce583c40dfb68c79
---
M Makefile.inc
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M src/soc/intel/apollolake/Makefile.inc
A src/soc/intel/apollolake/sample.fmd
M src/southbridge/intel/common/firmware/Makefile.inc
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61922 )
Change subject: soc/apollolake: Add support for creating IFWI images
......................................................................
Patch Set 9: Code-Review-1
(1 comment)
Patchset:
PS9:
You should probably have a discussion on the ML about integrating closed tooling. I personally don't think it's good idea to have in the master branch. I proposed something similar some time ago: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/message/F4T… . It's a somewhat different problem in the sense that there was an NDA blocking the release of code that was intended to be opened from the beginning. The upshot of that discussion was that's frowned upon by some/many in the community and also is technically problematic to maintain and even use.
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