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Change subject: vendorcode/intel/edk2/edk2-stable202111: Use fixed size struct elements
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
File src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/FspEas/FspApi.h:
https://review.coreboot.org/c/coreboot/+/62847/comment/83d7abe9_188def2d
PS1, Line 147: UINT32
I swear I brought this up to Nate before, that we should use fixed-size elements for ABIs, never `void *`...
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Change subject: mb/google/dedede/var/beadrix: Update PCIe and SATA pins for low power consumption
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62776/comment/a7c109e4_5902cdef
PS2, Line 11: After we disable unused PCIe and SATA
: pins, the measured power consumption meets Intel reuqired low power
: consumption.
> Please document the exact numbers.
Hi Paul,
Thank you for your advice.
+ Original measured high power consumption ~ 250 mW
"According to back and forth mail communication, so far ECS can't enter S0ix successfully and still under debugging (Power consumption is around 250mw)."
(https://partnerissuetracker.corp.google.com/issues/216050967#comment1)
+ After apply this CL, as well as, the other CL of MUX (3487086: USB MUX: Update low power mode of MUX anx7447 used as MUX only | https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3487086), measured power consumption, at S0ix of power state, achieves:
1. Wifi RTL8822 => measured ~110 mW
2. Wifi AX201 (higher power) => measured ~116 mW
+ Google battery lifetime requiremnt at S0ix of power state:
"Starting with a fully-charged battery, the Chrome device MUST remain operational for 14 days in the Suspend state. This state is S0ix or S3."
(https://chromeos.google.com/partner/dlm/docs/latest-requirements/chromebook…)
+ Intel power consumption requiremnt:
< 116 mW
(42000 mWh * 0.93 % (measured battery capacity)) / (14 days * 24 hrs) = 116.25 mW
+ As a result, I also update commit message.
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Change subject: soc/intel/adl: Remove IOM Mctp command from TCSS ASL
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/alderlake/acpi/tcss.asl:
https://review.coreboot.org/c/coreboot/+/62861/comment/90a43de7_c5a34947
PS2, Line 725: /*
: * If the TCSS Deven in normal state, then Save current TCSS DEVEN value and
: * clear it.
: */
: Local0 = 0
: While (\_SB.PCI0.TXHC.VDID != 0xFFFFFFFF) {
: If (DSGS () == 0) {
: DSCR (1)
: }
: Local0++
: If (Local0 == 5) {
: Printf("pCode mailbox command failed.")
: Break
: }
: }
> yes, they are not needed. Maulik, i think you can remove them.
Which means DSGS and DSCR are also unused now too I think
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Change subject: soc/mediatek: Pass dram info to cbmem
......................................................................
Patch Set 22:
(1 comment)
File src/soc/mediatek/common/memory.c:
https://review.coreboot.org/c/coreboot/+/61334/comment/bf277ba3_b9da65c9
PS22, Line 123: p = (void *)((uintptr_t)mc + sizeof(*mc));
> Maybe we should add a helper macro for this. […]
The C99 way was to declare as [], so compiler knows there's no fixed boundary.
Linux has already moved to C99, I wonder if Coreboot will also consider C99?
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Change subject: soc/mediatek: Pass dram info to cbmem
......................................................................
Patch Set 22:
(1 comment)
File src/soc/mediatek/common/memory.c:
https://review.coreboot.org/c/coreboot/+/61334/comment/c0f6edb0_577a8e7b
PS22, Line 123: p = (void *)((uintptr_t)mc + sizeof(*mc));
> It is written this way intentionally, to avoid the "subscript above array bounds" error (due to -Wer […]
Maybe we should add a helper macro for this.
#define member_array(ptr, member) ( \
check_member(__typeof__(*ptr), member, sizeof(*ptr));
(__typeof__(__typeof__(ptr->member[0]) *) ((uintptr_t)ptr + sizeof(*ptr)));
)
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Change subject: src/mediatek/mt8186: Get dram size from mtk ddr info or CBMEM_ID_MEMINFO
......................................................................
Patch Set 15:
(1 comment)
File src/soc/mediatek/common/include/soc/emi.h:
https://review.coreboot.org/c/coreboot/+/62065/comment/3fa25550_722c040a
PS15, Line 9: size_t mtk_dram_size(void); /* MTK dram size internal interface */
This should be added in the previous CL. No need for comments.
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Change subject: mb/google/brya/var/volmar: Disable thunderbolt
......................................................................
Patch Set 7:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62810/comment/953210d1_4342590c
PS5, Line 10: .The
> Please add a space.
fixed.
https://review.coreboot.org/c/coreboot/+/62810/comment/974a07b9_0deb76aa
PS5, Line 10: The volmar fit image had been disabled already,
: refer to chrome-internal:4459289
> Maybe: […]
fixed.
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Change subject: mb/google/brya/var/volmar: Disable thunderbolt
......................................................................
mb/google/brya/var/volmar: Disable thunderbolt
Volmar does not support Thunderbolt, therefore disable all of the TBT
devices in the devicetree. The volmar fit image had been disabled already, cf. chrome-internal:4459289.
BUG=b:2233193
TEST=Build and run on DUT.
Change-Id: Ic1bba80707b1d4a97c486e22f79feccf6241865e
Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/volmar/overridetree.cb
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/62810/7
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya/var/volmar: Disable thunderbolt
......................................................................
mb/google/brya/var/volmar: Disable thunderbolt
Volmar does not support Thunderbolt, therefore disable all of the TBT
devices in the devicetree. The volmar fit image had been disabled already,
cf. chrome-internal:4459289.
BUG=b:2233193
TEST=Build and run on DUT.
Change-Id: Ic1bba80707b1d4a97c486e22f79feccf6241865e
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---
M src/mainboard/google/brya/variants/volmar/overridetree.cb
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/62810/6
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Change subject: soc/mediatek: Pass dram info to cbmem
......................................................................
Patch Set 22:
(3 comments)
File src/soc/mediatek/common/memory.c:
https://review.coreboot.org/c/coreboot/+/61334/comment/f166bbc6_4c8dd487
PS21, Line 110: MEM_CHIP_LPDDR4X
> Yes, all LP4X.
Ack
File src/soc/mediatek/common/memory.c:
https://review.coreboot.org/c/coreboot/+/61334/comment/e5577180_b59171b1
PS22, Line 123: p = (void *)((uintptr_t)mc + sizeof(*mc));
> If you want to do something like this, please use […]
It is written this way intentionally, to avoid the "subscript above array bounds" error (due to -Werror=array-bounds). We've seen a similar error in vboot (CL:3133544). However, I don't know why we don't have problems in https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr….
https://review.coreboot.org/c/coreboot/+/61334/comment/3fff7b8a_fca00e94
PS22, Line 131: ++p;
> Please don't run two variables through the same loop unless really necessary. […]
Like I said above, unfortunately we cannot write it this way. I'd suggest using `p[i]` here.
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Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>
Comment-In-Reply-To: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com>
Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>
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