coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

1 participants
6700 discussions

Change in coreboot[master]: soc/qualcomm/common: Add dram information to CBMEM table
by Julius Werner (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Ravi kumar. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59195 ) Change subject: soc/qualcomm/common: Add dram information to CBMEM table ...................................................................... Patch Set 42: (5 comments) Patchset: PS42: Argh... this is what I get for typing too slowly. This CL is broken in several ways, please submit a follow-up patch shortly. File src/soc/qualcomm/common/qclib.c: https://review.coreboot.org/c/coreboot/+/59195/comment/ba81bfde_6b1d4bf3 PS41, Line 37: if (sizeof(struct mem_chip_info) != 0) What is this supposed to test, this can never be false? The thing you were supposed to check is `(te->size == sizeof(struct mem_chip_info))` up there in write_mem_chip_information(), and if not you don't set the mem_chip_addr pointer. Except that now since we changed the channels array in struct mem_chip_info to [0] (instead of [2]), that test needs to be a little more complicated: `(te->size > sizeof(struct mem_chip_info) && te->size == mem_chip_info_size((void *)te->blob_address)` (see below for mem_chip_info_size()). And then here in this function you should have if (!mem_chip_addr) { printk(BIOS_ERR, "Did not receive valid mem_chip_info from QcLib!"); return; } https://review.coreboot.org/c/coreboot/+/59195/comment/e14f4ed9_3031295f PS41, Line 39: sizeof(struct mem_chip_info) This is no longer correct now because we changed the declaration of the channels array in struct mem_chip_info from [2] to [0]. We need a way to determine the total size of a mem_chip_info in multiple places... it's probably worth adding a helper function to mem_chip_info.h for that: size_t mem_chip_info_size(struct mem_chip_info *info) { return sizeof(*info) + sizeof(info->channels[0]) * info->num_channels; }; https://review.coreboot.org/c/coreboot/+/59195/comment/26e5d093_4aba453a PS41, Line 43: sizeof(struct mem_chip_info) Same here. https://review.coreboot.org/c/coreboot/+/59195/comment/c224acae_f124ba0b PS41, Line 174: mem_chip_addr, sizeof(mem_chip_addr) This was supposed to be NULL and 0, and the comment above should clarify that the blob_address for this entry will be overwritten by QcLib to point to an info struct that it allocates itself. -- To view, visit https://review.coreboot.org/c/coreboot/+/59195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7 Gerrit-Change-Number: 59195 Gerrit-PatchSet: 42 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-CC: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Comment-Date: Thu, 17 Mar 2022 00:44:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/block: Add Intel common UFS code support
by Kangheui Won (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Rizwan Qureshi, Meera Ravindranath. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62855 ) Change subject: soc/intel/common/block: Add Intel common UFS code support ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: It looks like we don't have any specialized method in dev_ops, why can't we just use generic pci driver? -- To view, visit https://review.coreboot.org/c/coreboot/+/62855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92f034ced64e2eaef41a7807133361d74b5009d3 Gerrit-Change-Number: 62855 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Daniil Lunev <dlunev(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Comment-Date: Wed, 16 Mar 2022 23:57:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake: Add support for UFS controller
by Kangheui Won (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Tim Wawrzynczak, Rizwan Qureshi, Meera Ravindranath. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62856 ) Change subject: soc/intel/alderlake: Add support for UFS controller ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/62856/comment/1c5eb0cc_43b8e876 PS1, Line 619: s_cfg->UfsEnable[1] = 0; As I commented on CB:62662 I don't understand whyt this is array and why we're using index 1 here. Comments on FspsUpd.h seems wrong not helping anything. -- To view, visit https://review.coreboot.org/c/coreboot/+/62856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92f024ded64e1eaef41a7807133361d74b5009d4 Gerrit-Change-Number: 62856 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Daniil Lunev <dlunev(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Comment-Date: Wed, 16 Mar 2022 23:50:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/qualcomm/common: Add dram information to CBMEM table
by 9elements QA (Code Review) 17 Mar '22

17 Mar '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59195 ) Change subject: soc/qualcomm/common: Add dram information to CBMEM table ...................................................................... Patch Set 42: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/95970 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/95969 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/95968 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/95967 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/95966 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/95965 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/95964 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/95963 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/95962 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/95961 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/95960 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/95959 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/95958 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/95957 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/95956 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/95955 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/59195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7 Gerrit-Change-Number: 59195 Gerrit-PatchSet: 42 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-CC: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Comment-Date: Wed, 16 Mar 2022 23:41:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/nissa/var/nivviks: Add TcssAuxori for nivviks
by Reka Norman (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Kangheui Won, Paul Menzel, Tim Wawrzynczak, Usha P. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62731 ) Change subject: mb/google/nissa/var/nivviks: Add TcssAuxori for nivviks ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/nivviks/overridetree.cb: https://review.coreboot.org/c/coreboot/+/62731/comment/ee317ac5_cdad0d73 PS2, Line 12: register "TcssAuxOri" = "5" > +1. Even better if you can also add some information as comments. There's an explanation of the bitfield here: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… So I assume the 5 is because we don't have external retimers for ports C0 and C1? But yes, I agree a comment in the code would be nice. -- To view, visit https://review.coreboot.org/c/coreboot/+/62731 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I219de6092ac9a9c773adbaa99f5a7d6196a2c937 Gerrit-Change-Number: 62731 Gerrit-PatchSet: 2 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: harsha.b.r(a)intel.com Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Wed, 16 Mar 2022 23:40:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kangheui Won <khwon(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek: Pass dram info to cbmem
by Julius Werner (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Hung-Te Lin, Xi Chen, Paul Menzel, Xixi Chen. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61334 ) Change subject: soc/mediatek: Pass dram info to cbmem ...................................................................... Patch Set 22: (2 comments) File src/soc/mediatek/common/memory.c: https://review.coreboot.org/c/coreboot/+/61334/comment/d2d4ca29_8228cc51 PS22, Line 123: p = (void *)((uintptr_t)mc + sizeof(*mc)); If you want to do something like this, please use p = mc->channel; or p = &mc->channel[0]; instead of raw address arithmetic. https://review.coreboot.org/c/coreboot/+/61334/comment/bf669a2b_17480602 PS22, Line 131: ++p; Please don't run two variables through the same loop unless really necessary. In this case, you can either write for (p = mc->channel; p < &mc->channel[mc->num_channels]; p++) or you just access `mc->channel[i].density` inside the loop and then you won't have any of these headaches from trying to get a pointer to the channel struct. -- To view, visit https://review.coreboot.org/c/coreboot/+/61334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a Gerrit-Change-Number: 61334 Gerrit-PatchSet: 22 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Wed, 16 Mar 2022 23:37:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: x86: mmio: Qualify variables as volatile
by Julius Werner (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Paul Menzel. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62828 ) Change subject: x86: mmio: Qualify variables as volatile ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > There is no garantee in the C standard that '(type *)CONSTANT' will actually point to the hardware address 'CONSTANT'. It's just how gcc happens to do it in most cases. [https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99578#c29] That's it, folks, the GCC developers have now completely lost their minds as well. There's officially no sane compiler left. Declaring these pointer arguments as volatile has no real meaning in C and is really "wrong" from a theoretical standpoint. Personally, I think I'd prefer if we could wait with uprevving to GCC 11+ until they hopefully have found their senses again and implemented a flag to disable this crap, if we should be so lucky. Or is maybe setting -Wno-array-bounds for a while an option? How useful is that warning? However, if we want to stick to this then please at least clarify in the commit message that this is a workaround for a GCC bug, not a real fix. And add a comment to mmio.h to point to the bug so we might maybe one day have a chance to revert this back out. -- To view, visit https://review.coreboot.org/c/coreboot/+/62828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2769bb0e365aa9d82d709d3715323819bc9de6e Gerrit-Change-Number: 62828 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 16 Mar 2022 23:19:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/guybrush: Enable PSP_POSTCODES_ON_ESPI config
by Karthik Ramasubramanian (Code Review) 17 Mar '22

17 Mar '22

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62881 ) Change subject: mb/google/guybrush: Enable PSP_POSTCODES_ON_ESPI config ...................................................................... mb/google/guybrush: Enable PSP_POSTCODES_ON_ESPI config Guybrush uses ESPI to write postcodes and hence enable it. BUG=b:224543620 TEST=Build and boot to OS in Nipperkin. Ensure that there are no attempts to write postcodes from PSP verstage before ESPI initialization. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: Ic3930a037d37275c4130004079cd1afedcc13356 --- M src/mainboard/google/guybrush/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/62881/1 diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index b2cba6e..dc00c13 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -44,6 +44,7 @@ select PCIEXP_COMMON_CLOCK select PCIEXP_L1_SUB_STATE select PSP_DISABLE_POSTCODES if !VBOOT_STARTS_BEFORE_BOOTBLOCK + select PSP_POSTCODES_ON_ESPI if VBOOT_STARTS_BEFORE_BOOTBLOCK select PSP_S0I3_RESUME_VERSTAGE if VBOOT_STARTS_BEFORE_BOOTBLOCK select SOC_AMD_CEZANNE select SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF -- To view, visit https://review.coreboot.org/c/coreboot/+/62881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3930a037d37275c4130004079cd1afedcc13356 Gerrit-Change-Number: 62881 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/amd/common/psp_verstage: Write postcodes after ESPI init
by Karthik Ramasubramanian (Code Review) 17 Mar '22

17 Mar '22

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62880 ) Change subject: soc/amd/common/psp_verstage: Write postcodes after ESPI init ...................................................................... soc/amd/common/psp_verstage: Write postcodes after ESPI init On boards where PSP uses ESPI to write postcodes, update the verstage to do it after ESPI initialization. BUG=b:224543620 TEST=Build and boot to OS in Nipperkin. Ensure that there are no attempts to write the post code from PSP verstage before ESPI initialization. Change-Id: I1b78931c741c75dc845c9b34e3b2b896221f2364 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/common/psp_verstage/psp_verstage.c 2 files changed, 15 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/62880/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 81cf974..39b8db3 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -345,6 +345,13 @@ help Disables the output of port80 post codes from PSP. +config PSP_POSTCODES_ON_ESPI + bool "Use eSPI bus for PSP post codes" + depends on !PSP_DISABLE_POSTCODES + help + Select to send PSP port80 post codes on eSPI bus. + If not selected, PSP port80 codes will be sent on LPC bus. + config PSP_INIT_ESPI bool "Initialize eSPI in PSP Stage 2 Boot Loader" help diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 9d0fb22..d64c257 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -206,16 +206,21 @@ /* * Do not use printk() before console_init() * Do not use post_code() before verstage_mainboard_init() + * Do not use svc_write_postcode before verstage_soc_espi_init() if PSP uses ESPI + * to write postcodes. */ timestamp_init(timestamp_get()); - svc_write_postcode(POSTCODE_ENTERED_PSP_VERSTAGE); + if (!CONFIG(PSP_POSTCODES_ON_ESPI)) + svc_write_postcode(POSTCODE_ENTERED_PSP_VERSTAGE); svc_debug_print("Entering verstage on PSP\n"); memset(&_bss_start, '\0', &_bss_end - &_bss_start); - svc_write_postcode(POSTCODE_CONSOLE_INIT); + if (!CONFIG(PSP_POSTCODES_ON_ESPI)) + svc_write_postcode(POSTCODE_CONSOLE_INIT); console_init(); - svc_write_postcode(POSTCODE_EARLY_INIT); + if (!CONFIG(PSP_POSTCODES_ON_ESPI)) + svc_write_postcode(POSTCODE_EARLY_INIT); retval = verstage_soc_early_init(); if (retval) { /* -- To view, visit https://review.coreboot.org/c/coreboot/+/62880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b78931c741c75dc845c9b34e3b2b896221f2364 Gerrit-Change-Number: 62880 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/qualcomm/common: Add dram information to CBMEM table
by Shelley Chen (Code Review) 17 Mar '22

17 Mar '22

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59195 ) Change subject: soc/qualcomm/common: Add dram information to CBMEM table ...................................................................... soc/qualcomm/common: Add dram information to CBMEM table BUG=b:182963902,b:177917361 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59195 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shelley Chen <shchen(a)google.com> --- M src/soc/qualcomm/common/include/soc/qclib_common.h M src/soc/qualcomm/common/qclib.c 2 files changed, 35 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Shelley Chen: Looks good to me, approved diff --git a/src/soc/qualcomm/common/include/soc/qclib_common.h b/src/soc/qualcomm/common/include/soc/qclib_common.h index c906ef2..648b29d 100644 --- a/src/soc/qualcomm/common/include/soc/qclib_common.h +++ b/src/soc/qualcomm/common/include/soc/qclib_common.h @@ -22,6 +22,7 @@ #define QCLIB_TE_DDR_TRAINING_DATA "ddr_training_data" #define QCLIB_TE_LIMITS_CFG_DATA "limits_cfg_data" #define QCLIB_TE_QCSDI "qcsdi" +#define QCLIB_TE_MEM_CHIP_INFO "mem_chip_info" /* BA_BMASK_VALUES (blob_attributes bit mask values) */ #define QCLIB_BA_SAVE_TO_STORAGE 0x00000001 diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index e016f25..9a485db 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -16,9 +16,35 @@ #include <soc/symbols_common.h> #include <security/vboot/misc.h> #include <vb2_api.h> +#include <commonlib/bsd/mem_chip_info.h> #define QCLIB_VERSION 0 +/* store QcLib return data until ROMSTAGE_CBMEM_INIT_HOOK runs */ +static void *mem_chip_addr; + +static void write_mem_chip_information(struct qclib_cb_if_table_entry *te) +{ + /* Save mem_chip_info in local variables ahead of hook running */ + mem_chip_addr = (void *)te->blob_address; +} + +static void add_mem_chip_info(int unused) +{ + void *mem_region_base = NULL; + + /* Add cbmem table */ + if (sizeof(struct mem_chip_info) != 0) + mem_region_base = cbmem_add(CBMEM_ID_MEM_CHIP_INFO, + sizeof(struct mem_chip_info)); + ASSERT(mem_region_base != NULL); + + /* Migrate the data into CBMEM */ + memcpy(mem_region_base, mem_chip_addr, sizeof(struct mem_chip_info)); +} + +ROMSTAGE_CBMEM_INIT_HOOK(add_mem_chip_info); + struct qclib_cb_if_table qclib_cb_if_table = { .magic = QCLIB_MAGIC_NUMBER, .version = QCLIB_INTERFACE_VERSION, @@ -87,6 +113,10 @@ write_qclib_log_to_cbmemc(te); + } else if (!strncmp(QCLIB_TE_MEM_CHIP_INFO, te->name, + sizeof(te->name))) { + write_mem_chip_information(te); + } else { printk(BIOS_WARNING, "%s write not implemented\n", te->name); @@ -139,6 +169,10 @@ qclib_add_if_table_entry(QCLIB_TE_DDR_TRAINING_DATA, _ddr_training, REGION_SIZE(ddr_training), 0); + /* Attempt to read MEM CHIP information */ + qclib_add_if_table_entry(QCLIB_TE_MEM_CHIP_INFO, + mem_chip_addr, sizeof(mem_chip_addr), 0); + /* Attempt to load PMICCFG Blob */ data_size = cbfs_load(CONFIG_CBFS_PREFIX "/pmiccfg", _pmic, REGION_SIZE(pmic)); -- To view, visit https://review.coreboot.org/c/coreboot/+/59195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7 Gerrit-Change-Number: 59195 Gerrit-PatchSet: 42 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-CC: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-MessageType: merged

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2022