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Change subject: soc/mediatek: Save dram info to cbmem
......................................................................
Patch Set 25:
(1 comment)
File src/soc/mediatek/common/memory.c:
https://review.coreboot.org/c/coreboot/+/61334/comment/9899c380_8fd87663
PS22, Line 123: p = (void *)((uintptr_t)mc + sizeof(*mc));
> > If &mc->channel[0] does not work, what about "p = mc->channel" ? […]
hmm, it worked for my local clang with default options. maybe coreboot has a different compilation setting.
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Change subject: mb/google: Remove unused cpu device
......................................................................
Patch Set 1: Code-Review+1
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Change subject: soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code
......................................................................
Patch Set 12:
(5 comments)
File src/soc/intel/common/block/pmc/Kconfig:
https://review.coreboot.org/c/coreboot/+/62064/comment/c9cf1c41_8a26afe1
PS12, Line 13: GEN_PMCON_A
> At least drop the _A, since both _A and _B were moved. […]
Ack
File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/62064/comment/fc11af3a_3fc8b51c
PS9, Line 634: && (GEN_PMCON_A <= 0xff)
> > > Trying to avoid SoC name in common code, once added then it will become as a trend like Intel FSP, where common code does the SoC check 😞
> >
> > Agreed
> >
> > > I'm trying to add new Kconfig due to maintenance and added the big comment section to explain what is the reason for this additional check.
> >
> > I guess you meant `avoid`?
>
> yes 😊
>
> >
> > Is it really that much maintenance?
>
> Not sure, I agree. Let see, I have attempted to create one, let me know your feedback.
Marking this resolve now. Please let me know if you think it's not addressed in proper.
File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/62064/comment/599e1010_c382112b
PS12, Line 614: * And, the PMC device is visible over the PCI bus, so the SoC user selects
: * `SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE` Kconfig.
:
> with the new Kconfig this doesn't matter anymore, does it?
Ack
https://review.coreboot.org/c/coreboot/+/62064/comment/37584eca_17d6cad7
PS12, Line 617: * And, the PMC device is not over the PCI bus and hidden by the FSP.
> same as 617
Ack
https://review.coreboot.org/c/coreboot/+/62064/comment/5530ded3_59abe060
PS12, Line 619: * Using SOC_INTEL_MEM_MAPPED_GEN_PMCON_A Kconfig to perform GEN_PMCON_A register
: * programming.
:
> doesn't provide any additional information, does ot?
Ack
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Hello Felix Singer, build bot (Jenkins), Jeff Daly, Mariusz Szafrański, Jonathan Zhang, Angel Pons, Arthur Heymans, Michael Niewöhner, Andrey Petrov, Patrick Rudolph, Anjaneya "Reddy" Chagam, Johnny Lin, Christian Walter, Suresh Bellampalli, Tim Wawrzynczak, Vanessa Eusebio, Nick Vaccaro, siemens-bot, Lean Sheng Tan, Michal Motyl, Werner Zeh, Tim Chu,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code
......................................................................
soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code
This patch moves `pmc_clear_pmcon_sts` function into common code and
remove SoC specific instances.
Accessing PMC GEN_PMCON_A register differs between different Intel
chipsets. Typically, there are two possible ways to perform GEN_PMCON_A
register programming (like `pmc_clear_pmcon_sts()`) as:
1. Using PCI configuration space when GEN_PMCON_A is a PCI configuration
register.
2. Using MMIO access when GEN_PMCON_A is a memory mapped register.
SoC users to select `SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION` Kconfig to
perform GEN_PMCON_A register programming using PMC MMIO.
BUG=b:211954778
TEST=Able to build brya.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/include/soc/pm.h
M src/soc/intel/alderlake/pmutil.c
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/apollolake/include/soc/pm.h
M src/soc/intel/apollolake/pmutil.c
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/include/soc/pm.h
M src/soc/intel/cannonlake/pmutil.c
M src/soc/intel/common/block/include/intelblocks/pmclib.h
M src/soc/intel/common/block/pmc/Kconfig
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/pmc/pmclib.c
M src/soc/intel/denverton_ns/include/soc/pm.h
M src/soc/intel/denverton_ns/pmutil.c
M src/soc/intel/elkhartlake/Kconfig
M src/soc/intel/elkhartlake/include/soc/pm.h
M src/soc/intel/elkhartlake/pmutil.c
M src/soc/intel/icelake/Kconfig
M src/soc/intel/icelake/include/soc/pm.h
M src/soc/intel/icelake/pmutil.c
M src/soc/intel/jasperlake/Kconfig
M src/soc/intel/jasperlake/include/soc/pm.h
M src/soc/intel/jasperlake/pmutil.c
M src/soc/intel/skylake/include/soc/pm.h
M src/soc/intel/skylake/pmutil.c
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/include/soc/pm.h
M src/soc/intel/tigerlake/pmutil.c
M src/soc/intel/xeon_sp/include/soc/pm.h
M src/soc/intel/xeon_sp/pmutil.c
31 files changed, 57 insertions(+), 173 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/62064/13
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Change subject: mb/google/nissa/var/nivviks: Add TcssAuxori for nivviks
......................................................................
Patch Set 5:
(3 comments)
Patchset:
PS5:
It can be a separate patch if you want, but do we need the same for nereid?
File src/mainboard/google/brya/variants/nivviks/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/62731/comment/c8489044_cfeb8575
PS5, Line 12: ,b
nit: add a space
https://review.coreboot.org/c/coreboot/+/62731/comment/16e77931_4e4af527
PS5, Line 13: #l
nit: add a space
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Change subject: soc/intel/common/block/p2sb: Add helper function to enable BAR
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> Just curious why need this in bootblock and romstage?
It's to compliment p2sb.c and ioe_p2sb.c file which has added for all stages but library code (p2sblib.c) only added for later stage.
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Change subject: mb/google/brya/var/banshee: Update DPTF parameters
......................................................................
Patch Set 2: Code-Review+2
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Change subject: drivers/wifi/generic: Fix properties in generic-under-PCI device case
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Patch Set 4: Code-Review+1
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Change subject: mb/google/brya/variants/crota: set up gpio
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Patch Set 7:
(1 comment)
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https://review.coreboot.org/c/coreboot/+/62854/comment/ad05fd11_9d8a1871
PS3, Line 9: Set the GPIO configuration of crota
> Please mention the source.
Upload the schematic on b/219891328
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Change subject: mb/google/brya/variants/crota: set up gpio
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