coreboot-gerrit March 2022

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Change in coreboot[master]: soc/intel/common/block/p2sb: Add helper function to enable BAR
by Eric Lai (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Wonkyu Kim, Subrata Banik, Tim Wawrzynczak, John Zhao, Angel Pons, Nick Vaccaro, Patrick Rudolph. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62778 ) Change subject: soc/intel/common/block/p2sb: Add helper function to enable BAR ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Just curious why need this in bootblock and romstage? -- To view, visit https://review.coreboot.org/c/coreboot/+/62778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica41e8e8bdfcfe855e730b3878b874070062ef93 Gerrit-Change-Number: 62778 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 17 Mar 2022 06:08:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/p2sb: Add helper function to enable BAR
by Eric Lai (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Wonkyu Kim, Subrata Banik, Tim Wawrzynczak, John Zhao, Angel Pons, Nick Vaccaro, Patrick Rudolph. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62778 ) Change subject: soc/intel/common/block/p2sb: Add helper function to enable BAR ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica41e8e8bdfcfe855e730b3878b874070062ef93 Gerrit-Change-Number: 62778 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 17 Mar 2022 06:07:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/banshee: Update DPTF parameters
by Frank Wu (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: John Su, YH Lin, Dtrain Hsu, Paul Menzel, Ricky Chang. Frank Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62807 ) Change subject: mb/google/brya/var/banshee: Update DPTF parameters ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Hi Tim, Could you help CR+2 since Sumeet already reviewed it? Thank you. -- To view, visit https://review.coreboot.org/c/coreboot/+/62807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5da776e7ae3368ce00cd29ec0ccdb5b7a725ff88 Gerrit-Change-Number: 62807 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ricky Chang <rickytlchang(a)google.com> Gerrit-Comment-Date: Thu, 17 Mar 2022 06:07:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/mediatek/mt8186: Implement sdram_size() to get real dram size
by Yu-Ping Wu (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Hung-Te Lin, Xixi Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62065 ) Change subject: src/mediatek/mt8186: Implement sdram_size() to get real dram size ...................................................................... Patch Set 19: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I017e9d1a2d6e26f1fc21b67b5962dfb5c6ade8a5 Gerrit-Change-Number: 62065 Gerrit-PatchSet: 19 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Thu, 17 Mar 2022 06:06:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl: Remove IOM Mctp command from TCSS ASL
by Kane Chen (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Shobhit Srivastava, Subrata Banik, Maulik V Vaghela, Kane Chen, Tim Wawrzynczak. Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62861 ) Change subject: soc/intel/adl: Remove IOM Mctp command from TCSS ASL ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f066bcc4a8f475a15ddd12ef5ed87d7298312bb Gerrit-Change-Number: 62861 Gerrit-PatchSet: 3 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Shobhit Srivastava <shobhit.srivastava(a)intel.com> Gerrit-Reviewer: Shobhit Srivastava <shobhit.srivastava(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shobhit Srivastava <shobhit.srivastava(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 17 Mar 2022 06:03:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/mediatek/mt8186: Implement sdram_size() to get real dram size
by build bot (Jenkins) (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62065 ) Change subject: src/mediatek/mt8186: Implement sdram_size() to get real dram size ...................................................................... Patch Set 18: Verified+1 (1 comment) File src/soc/mediatek/mt8186/emi.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144164): https://review.coreboot.org/c/coreboot/+/62065/comment/9e2b4297_6ee7da7d PS18, Line 29: for (unsigned int i = 0; i < mc->num_channels; ++i) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/62065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I017e9d1a2d6e26f1fc21b67b5962dfb5c6ade8a5 Gerrit-Change-Number: 62065 Gerrit-PatchSet: 18 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 17 Mar 2022 06:02:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/cpu: Enable ROM caching in ramstage
by Subrata Banik (Code Review) 17 Mar '22

17 Mar '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62838 ) Change subject: soc/intel/common/block/cpu: Enable ROM caching in ramstage ...................................................................... soc/intel/common/block/cpu: Enable ROM caching in ramstage Cache the BIOS region and extended BIOS region if the boot device is memory mapped, which is mostly the case with Intel SoC platform. Having the ROM region cached helped to improve the pre-boot time. TEST=Able to boot redrix to Chrome OS without seeing any sluggishness. Additionally verified on EHL board (from siemens), shows significant savings in payload loading time as below: Here is the timestamp snippet showing the payload load time as a comparison between current upstream and the patched version: upstream: 90:starting to load payload 1,072,459 (1,802) 958:calling FspNotify(ReadyToBoot) 12,818,079 (11,745,619) with this patch: 90:starting to load payload 1,072,663 (2,627) 958:calling FspNotify(ReadyToBoot) 5,299,535 (4,226,871) Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I02b80eefbb3b19331698a205251a0c4d17be534c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62838 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/mp_init.c 1 file changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Arthur Heymans: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 99d9507..2d838c5 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -152,6 +152,14 @@ init_cpus(); } +static void post_cpus_add_romcache(void) +{ + if (!CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) + return; + + fast_spi_cache_bios_region(); +} + static void wrapper_x86_setup_mtrrs(void *unused) { x86_setup_mtrrs_with_detect(); @@ -163,6 +171,7 @@ if (mp_run_on_all_cpus(&wrapper_x86_setup_mtrrs, NULL) != CB_SUCCESS) printk(BIOS_ERR, "MTRR programming failure\n"); + post_cpus_add_romcache(); x86_mtrr_check(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/62838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02b80eefbb3b19331698a205251a0c4d17be534c Gerrit-Change-Number: 62838 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/fast_spi: support caching `ext_bios` in ramstage
by Subrata Banik (Code Review) 17 Mar '22

17 Mar '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62837 ) Change subject: soc/intel/common/fast_spi: support caching `ext_bios` in ramstage ...................................................................... soc/intel/common/fast_spi: support caching `ext_bios` in ramstage This patch provides a way to cache `ext_bios` region for all stages to save boot time. TEST=Able to see the ext_bios region in MTRR snapshot when cached on the Brya variants. Here is the timestamp snippet showing the payload load time as a comparison between current upstream and the patched version: upstream: 90:starting to load payload 1,072,459 (1,802) 958:calling FspNotify(ReadyToBoot) 12,818,079 (11,745,619) with this patch: 90:starting to load payload 1,072,663 (2,627) 958:calling FspNotify(ReadyToBoot) 5,299,535 (4,226,871) Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I87139a9ed7eb9ed43164a5199aa436dd1219145c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62837 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/fast_spi/fast_spi.c 1 file changed, 8 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Arthur Heymans: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 0e01231..7be71a2 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -245,10 +245,14 @@ if (!fast_spi_ext_bios_cache_range(&ext_bios_base, &ext_bios_size)) return; - int mtrr = get_free_var_mtrr(); - if (mtrr == -1) - return; - set_var_mtrr(mtrr, ext_bios_base, ext_bios_size, type); + if (ENV_PAYLOAD_LOADER) { + mtrr_use_temp_range(ext_bios_base, ext_bios_size, type); + } else { + int mtrr = get_free_var_mtrr(); + if (mtrr == -1) + return; + set_var_mtrr(mtrr, ext_bios_base, ext_bios_size, type); + } } void fast_spi_cache_ext_bios_postcar(struct postcar_frame *pcf) -- To view, visit https://review.coreboot.org/c/coreboot/+/62837 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87139a9ed7eb9ed43164a5199aa436dd1219145c Gerrit-Change-Number: 62837 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/fast_spi: support caching `ext_bios` in ramstage
by Subrata Banik (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Subrata Banik, Paul Menzel, Angel Pons, Nick Vaccaro, Eric Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62837 ) Change subject: soc/intel/common/fast_spi: support caching `ext_bios` in ramstage ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/block/fast_spi/fast_spi.c: https://review.coreboot.org/c/coreboot/+/62837/comment/ad8b94ed_4d3b2050 PS3, Line 248: if (ENV_PAYLOAD_LOADER) { : mtrr_use_temp_range(ext_bios_base, ext_bios_size, type); : } else { > potential optimization for the future: if the extended BIOS window is added into the list of memranges below before the MTRR calls in fast_spi_cache_bios_region(), then the MTRR solution only needs to be calculated one time instead of two. good suggestion. we need to refactor this code to combine the addresses. -- To view, visit https://review.coreboot.org/c/coreboot/+/62837 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87139a9ed7eb9ed43164a5199aa436dd1219145c Gerrit-Change-Number: 62837 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 17 Mar 2022 06:01:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: src/mediatek/mt8186: Implement sdram_size() to get real dram size
by Xixi Chen (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Xixi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62065 ) Change subject: src/mediatek/mt8186: Implement sdram_size() to get real dram size ...................................................................... Patch Set 18: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62065/comment/223c99f8_79a37864 PS17, Line 7: Get dram size from mtk ddr info or CBMEM_ID_MEMINFO > Implement sdram_size() to get real dram size Ack File src/soc/mediatek/mt8186/emi.c: https://review.coreboot.org/c/coreboot/+/62065/comment/8d3ab5f7_92091b3b PS15, Line 20: size = mtk_dram_size(); > No need, ramstage won't compile if (ENV_ROMSTAGE), the same to if (0). Done File src/soc/mediatek/mt8186/emi.c: https://review.coreboot.org/c/coreboot/+/62065/comment/df97a08d_5191a488 PS16, Line 21: ( > One space before "(" Ack https://review.coreboot.org/c/coreboot/+/62065/comment/122dbf30_f3b46f5a PS16, Line 29: { > Remove Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/62065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I017e9d1a2d6e26f1fc21b67b5962dfb5c6ade8a5 Gerrit-Change-Number: 62065 Gerrit-PatchSet: 18 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 17 Mar 2022 06:01:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit March 2022