coreboot-gerrit March 2022

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Change in coreboot[master]: soc/mediatek: Save dram info to cbmem
by Xixi Chen (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Hung-Te Lin, Xi Chen, Paul Menzel, Julius Werner, Xixi Chen. Hello Xi Chen, Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61334 to look at the new patch set (#25). Change subject: soc/mediatek: Save dram info to cbmem ...................................................................... soc/mediatek: Save dram info to cbmem Store dram info in cbmem for payloads to use. BUG=b:206014043 TEST=Build pass on Kingler Signed-off-by: Xi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a --- M src/soc/mediatek/common/include/soc/emi.h M src/soc/mediatek/common/memory.c 2 files changed, 51 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/61334/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/61334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a Gerrit-Change-Number: 61334 Gerrit-PatchSet: 25 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek: Pass dram info to cbmem
by Yu-Ping Wu (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Hung-Te Lin, Xi Chen, Paul Menzel, Julius Werner, Xixi Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61334 ) Change subject: soc/mediatek: Pass dram info to cbmem ...................................................................... Patch Set 24: (1 comment) File src/soc/mediatek/common/memory.c: https://review.coreboot.org/c/coreboot/+/61334/comment/15a2fa47_51eb3477 PS24, Line 126: channel[i].density = size / mc->num_channels; Is 'size' always a multiple of num_channels? Otherwise, the sum of all channel[i].density may not be 'size'. -- To view, visit https://review.coreboot.org/c/coreboot/+/61334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a Gerrit-Change-Number: 61334 Gerrit-PatchSet: 24 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Thu, 17 Mar 2022 05:50:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/banshee: Replace amp max98357 with max98360
by Frank Wu (Code Review) 17 Mar '22

17 Mar '22

Frank Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62887 ) Change subject: mb/google/brya/var/banshee: Replace amp max98357 with max98360 ...................................................................... mb/google/brya/var/banshee: Replace amp max98357 with max98360 Based on the latest schematic, replace amp max98357 with max98360. BUG=b:224692387, b:216110896 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: Id265a4276c3f8b5553a0e5d7ed824b1d9a520d44 --- M src/mainboard/google/brya/variants/banshee/gpio.c M src/mainboard/google/brya/variants/banshee/overridetree.cb 2 files changed, 17 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/62887/1 diff --git a/src/mainboard/google/brya/variants/banshee/gpio.c b/src/mainboard/google/brya/variants/banshee/gpio.c index 75a2743..a6f6854 100644 --- a/src/mainboard/google/brya/variants/banshee/gpio.c +++ b/src/mainboard/google/brya/variants/banshee/gpio.c @@ -229,26 +229,29 @@ /* R1 : HDA_SYNC ==> I2S_HP_SFRM_R */ /* R2 : HDA_SDO ==> I2S_PCH_TX_HP_RX_STRAP */ /* R3 : HDA_SDIO ==> I2S_PCH_RX_HP_TX */ - /* R4 : HDA_RST# ==> I2S_SPKR_SCLK_R */ - /* R5 : HDA_SDI1 ==> I2S_SPKR_SFRM_R */ - /* R6 : I2S2_TXD ==> I2S_PCH_TX_SPKR_RX_R */ + /* R4 : HDA_RST# ==> NC */ + PAD_NC(GPP_R4, NONE), + /* R5 : HDA_SDI1 ==> NC */ + PAD_NC(GPP_R5, NONE), + /* R6 : I2S2_TXD ==> NC */ + PAD_NC(GPP_R6, NONE), /* R7 : I2S2_RXD ==> NC */ PAD_NC(GPP_R7, NONE), - /* S0 : SNDW0_CLK ==> NC */ - PAD_NC(GPP_S0, NONE), - /* S1 : SNDW0_DATA ==> NC */ - PAD_NC(GPP_S1, NONE), - /* S2 : SNDW1_CLK ==> DMIC_CLK0_R */ - /* S3 : SNDW1_DATA ==> DMIC_DATA0_R */ + /* S0 : SNDW0_CLK ==> I2S_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), + /* S1 : SNDW0_DATA ==> I2S_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), + /* S2 : SNDW1_CLK ==> I2S_PCH_TX_SPKR_RX_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), + /* S3 : SNDW1_DATA ==> NC */ + PAD_NC(GPP_S3, NONE), /* S4 : SNDW2_CLK ==> NC */ PAD_NC(GPP_S4, NONE), /* S5 : SNDW2_DATA ==> NC */ PAD_NC(GPP_S5, NONE), - /* S6 : SNDW3_CLK ==> NC */ - PAD_NC(GPP_S6, NONE), - /* S7 : SNDW3_DATA ==> NC */ - PAD_NC(GPP_S7, NONE), + /* S6 : SNDW3_CLK ==> DMIC_CLK0_R */ + /* S7 : SNDW3_DATA ==> DMIC_DATA0_R */ }; /* Early pad configuration in bootblock */ diff --git a/src/mainboard/google/brya/variants/banshee/overridetree.cb b/src/mainboard/google/brya/variants/banshee/overridetree.cb index 9601d05..f57ccf1 100644 --- a/src/mainboard/google/brya/variants/banshee/overridetree.cb +++ b/src/mainboard/google/brya/variants/banshee/overridetree.cb @@ -215,7 +215,7 @@ end device ref hda on chip drivers/generic/max98357a - register "hid" = ""MX98357A"" + register "hid" = ""MX98360A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" register "sdmode_delay" = "5" -- To view, visit https://review.coreboot.org/c/coreboot/+/62887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id265a4276c3f8b5553a0e5d7ed824b1d9a520d44 Gerrit-Change-Number: 62887 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/mediatek/mt8186: Get dram size from mtk ddr info or CBMEM_ID_MEMINFO
by Yu-Ping Wu (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Hung-Te Lin, Xixi Chen, Yu-Ping Wu. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62065 ) Change subject: src/mediatek/mt8186: Get dram size from mtk ddr info or CBMEM_ID_MEMINFO ...................................................................... Patch Set 16: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62065/comment/efbe9b00_3ea7bae6 PS14, Line 10: should update from > calculate it from the mem chip info stored in Done https://review.coreboot.org/c/coreboot/+/62065/comment/d0cc4f65_27663cad PS14, Line 13: TEST=Build pass on Kingler > Did you see the correct "dram size: ... […] Done File src/soc/mediatek/mt8186/emi.c: https://review.coreboot.org/c/coreboot/+/62065/comment/3d2d7955_8f073020 PS14, Line 16: p > channel Done https://review.coreboot.org/c/coreboot/+/62065/comment/fa0f9cc1_bc482938 PS14, Line 17: uint64_t > size_t Done https://review.coreboot.org/c/coreboot/+/62065/comment/e1646e17_4f034d60 PS14, Line 20: != NULL > Remove Done File src/soc/mediatek/mt8186/emi.c: https://review.coreboot.org/c/coreboot/+/62065/comment/486244cb_d6f1c8a5 PS16, Line 21: ( One space before "(" https://review.coreboot.org/c/coreboot/+/62065/comment/9386ae49_d2378375 PS16, Line 29: { Remove -- To view, visit https://review.coreboot.org/c/coreboot/+/62065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I017e9d1a2d6e26f1fc21b67b5962dfb5c6ade8a5 Gerrit-Change-Number: 62065 Gerrit-PatchSet: 16 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 17 Mar 2022 05:49:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Trigger wdt SW reset when wdt status is not equal to 0
by Rex-BC Chen (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62797 ) Change subject: soc/mediatek: Trigger wdt SW reset when wdt status is not equal to 0 ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: @yu-ping, please help to review. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/62797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6128df7eadaebcf7ff8d4c5492e3e0cfbab6e36 Gerrit-Change-Number: 62797 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 17 Mar 2022 05:46:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/mediatek/mt8186: Get dram size from mtk ddr info or CBMEM_ID_MEMINFO
by Xixi Chen (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Xixi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62065 ) Change subject: src/mediatek/mt8186: Get dram size from mtk ddr info or CBMEM_ID_MEMINFO ...................................................................... Patch Set 17: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62065/comment/80a77f11_dc4c52bd PS14, Line 10: should update from > calculate it from the mem chip info stored in Ack https://review.coreboot.org/c/coreboot/+/62065/comment/282ed393_6787968b PS14, Line 13: TEST=Build pass on Kingler > Did you see the correct "dram size: ... […] yes. File src/soc/mediatek/common/include/soc/emi.h: https://review.coreboot.org/c/coreboot/+/62065/comment/03a2a3a1_530ff3f3 PS15, Line 9: size_t mtk_dram_size(void); /* MTK dram size internal interface */ > This should be added in the previous CL. No need for comments. Ack File src/soc/mediatek/mt8186/emi.c: https://review.coreboot.org/c/coreboot/+/62065/comment/04e22090_c2808619 PS14, Line 16: p > channel Ack https://review.coreboot.org/c/coreboot/+/62065/comment/ed6b53c8_2cde221f PS14, Line 17: uint64_t > size_t Ack https://review.coreboot.org/c/coreboot/+/62065/comment/515c862d_89a7cd1a PS14, Line 20: != NULL > Remove Ack File src/soc/mediatek/mt8186/emi.c: https://review.coreboot.org/c/coreboot/+/62065/comment/198cf5be_38b129e9 PS15, Line 20: size = mtk_dram_size(); > Do we need to add memory.c to ramstage in Makefile. […] No need, ramstage won't compile if (ENV_ROMSTAGE), the same to if (0). -- To view, visit https://review.coreboot.org/c/coreboot/+/62065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I017e9d1a2d6e26f1fc21b67b5962dfb5c6ade8a5 Gerrit-Change-Number: 62065 Gerrit-PatchSet: 17 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 17 Mar 2022 05:46:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Trigger wdt SW reset when wdt status is not equal to 0
by Rex-BC Chen (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62797 ) Change subject: soc/mediatek: Trigger wdt SW reset when wdt status is not equal to 0 ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > wait for verify done -- To view, visit https://review.coreboot.org/c/coreboot/+/62797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6128df7eadaebcf7ff8d4c5492e3e0cfbab6e36 Gerrit-Change-Number: 62797 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 17 Mar 2022 05:46:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Trigger wdt SW reset when wdt status is not equal to 0
by Rex-BC Chen (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62797 ) Change subject: soc/mediatek: Trigger wdt SW reset when wdt status is not equal to 0 ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6128df7eadaebcf7ff8d4c5492e3e0cfbab6e36 Gerrit-Change-Number: 62797 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 17 Mar 2022 05:46:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Pass dram info to cbmem
by Yu-Ping Wu (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Hung-Te Lin, Xi Chen, Paul Menzel, Julius Werner, Yu-Ping Wu. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61334 ) Change subject: soc/mediatek: Pass dram info to cbmem ...................................................................... Patch Set 23: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61334/comment/087afc68_8465d32e PS23, Line 7: Pass Save https://review.coreboot.org/c/coreboot/+/61334/comment/c6f6bba6_866975fd PS23, Line 9: Pass dram_info struct from coreboot to depthcharge using payload. Store dram info in cbmem for payloads to use. -- To view, visit https://review.coreboot.org/c/coreboot/+/61334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a Gerrit-Change-Number: 61334 Gerrit-PatchSet: 23 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 17 Mar 2022 05:45:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Pass dram info to cbmem
by Xixi Chen (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Hung-Te Lin, Xi Chen, Paul Menzel, Julius Werner, Yu-Ping Wu. Xixi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61334 ) Change subject: soc/mediatek: Pass dram info to cbmem ...................................................................... Patch Set 24: (12 comments) File src/soc/mediatek/common/memory.c: https://review.coreboot.org/c/coreboot/+/61334/comment/d42b4307_d1690557 PS21, Line 29: curr_dram_info > Please remove this. Done https://review.coreboot.org/c/coreboot/+/61334/comment/2b7cbc40_23033102 PS21, Line 108: p > channel Done https://review.coreboot.org/c/coreboot/+/61334/comment/c7b8f42e_f62a9fa2 PS21, Line 108: p > channel Done https://review.coreboot.org/c/coreboot/+/61334/comment/339f9881_e0bf1cc6 PS21, Line 129: void *mem_region_base > struct mem_chip_info *mc; Done https://review.coreboot.org/c/coreboot/+/61334/comment/2ffaccfb_40d2bb2e PS21, Line 129: void *mem_region_base > struct mem_chip_info *mc; Done https://review.coreboot.org/c/coreboot/+/61334/comment/a6d9e69b_d6b962f8 PS21, Line 131: > Check if curr_ddr_info is NULL. already remove this https://review.coreboot.org/c/coreboot/+/61334/comment/9b996371_86bccae9 PS21, Line 132: curr_dram_info > *mc Done https://review.coreboot.org/c/coreboot/+/61334/comment/e1914e3b_4ea88f78 PS21, Line 134: ASSERT > assert(mc); Done https://review.coreboot.org/c/coreboot/+/61334/comment/bfbb4e63_d2d0d906 PS21, Line 217: ddr_info > The reason to rename to ddr_info is that when the first patch, the name of mem_chip_info is "dram_in […] Done File src/soc/mediatek/common/memory.c: https://review.coreboot.org/c/coreboot/+/61334/comment/2b8f0e64_7b743966 PS22, Line 104: size_t mtk_dram_size(void) > Need to declare this in emi.h. Done https://review.coreboot.org/c/coreboot/+/61334/comment/b8406dbe_4e86927a PS22, Line 107: > return 0 if !curr_ddr_info Done https://review.coreboot.org/c/coreboot/+/61334/comment/e707a543_8bf22962 PS22, Line 131: ++p; > Like I said above, unfortunately we cannot write it this way. I'd suggest using `p[i]` here. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/61334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a Gerrit-Change-Number: 61334 Gerrit-PatchSet: 24 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 17 Mar 2022 05:45:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit March 2022