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Change subject: drivers/smmstore: Enable 4KiB blocks in SMMSTORE
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Sorry dude, the logic is lost on me. If we don't change any defaults, someone selects an option that breaks something because they haven't read up on it, it's trial and error anyway - they'd just unselect it...
> Have you tried the following using native coreboot tools to edit the layout?
No, as it would break the manifest.
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Change subject: drivers/smmstore: Enable 4KiB blocks in SMMSTORE
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> > fix the payload
> Pandora's box, first thing they'll ask is why 64KiB - we dont want people to configure it wrong is a weak argument.
>
Having options to configure things is ok. Having options to configure things potentially incorrectly should be avoided.
A Kconfig to work around the failings of a specific payload makes using coreboot even more complicated than it already is. You'd need to understand a whole lot of things to be able to make a decision whether 4K or 64K block erase in SMMSTORE is a good idea for your payload. Your then essentially pushing responsibility from developer to users and we try to avoid that.
> Plus you've got to get past Patrick first :p
>
> > Can you not just top align the COREBOOT region in fmap and BIOS region in IFD to work around this?
> I can not, I have tried and failed - to the point of thinking it's impossible. I'd happily be proved wrong.
The Intel tooling does not seem to allow for that indeed. (it looks pretty bad in general ^^)
Have you tried the following using native coreboot tools to edit the layout?
$ util/ifdtool/ifdtool build/coreboot.bin -f /tmp/layout -p aplk
-> modify /tmp/layout so that BIOS region end is 64K aligned
$ util/ifdtool/ifdtool build/coreboot.bin -n /tmp/layout -p aplk
-> Now you have a worthless image but with a good ifd. extract it
$ util/ifdtool/ifdtool build/coreboot.bin -x
-> use that new IFD & adapt fmap and rebuild.
Totally untested btw, just a suggestion.
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Change subject: drivers/smmstore: Enable 4KiB blocks in SMMSTORE
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> fix the payload
Pandora's box, first thing they'll ask is why 64KiB - we dont want people to configure it wrong is a weak argument.
Plus you've got to get past Patrick first :p
> Can you not just top align the COREBOOT region in fmap and BIOS region in IFD to work around this?
I can not, I have tried and failed - to the point of thinking it's impossible. I'd happily be proved wrong.
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Change subject: drivers/smmstore: Enable 4KiB blocks in SMMSTORE
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Okay, so easy solution, make it a Kconfig option?
A user visibly one seems like a bad idea. You don't want things exposed that can be wrongly configured.
Even hidden ones selected by specific SPI drivers sounds messy and maybe even impossible as some vendors have chips that support 4K and 64K erase and there is no possibility to distinguish properly at a Kconfig level. I think the proper fix is to fix the payload, not to work around it in coreboot.
Can you not just top align the COREBOOT region in fmap and BIOS region in IFD to work around this?
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Change subject: drivers/smmstore: Enable 4KiB blocks in SMMSTORE
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> > It's this^ change, or this -https://github. […]
Okay, so easy solution, make it a Kconfig option?
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Change subject: drivers/smmstore: Enable 4KiB blocks in SMMSTORE
......................................................................
Patch Set 1:
(2 comments)
Patchset:
PS1:
> See https://github.com/coreboot/coreboot/blob/1f54599b9875e0de80c8636626bdfbe01…
>
> Not sure what the minimum flash sector size is on AMD or older platforms. Maybe this can be gathered from Kconfig/bootmedia API?
It depends on the coreboot driver for the flash chip see 'sector_size_kib_shift'. 64K is the smallest common denomination.
PS1:
> It's this^ change, or this -https://github.com/StarLabsLtd/edk2/commit/e5033f0e9a01c2d4288370ef25cb12f2ee0a339e
>
I'm not sure I understand that patch. It just looks like the block alignment check is broken in EDK2 and that 4K writes is just a workaround.
> The suggestion came from Patrick, to avoid the edk2 patches. It does not break erasing.
That depends on the flash chip you have installed. spi_flash_cmd_erase() will check the block erase size against the erase size arguments. So this would break some flash chips.
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Change subject: soc/amd/non_car/memlayout_x86.ld: Top aling the bootblock
......................................................................
Patch Set 1:
(2 comments)
File src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld:
https://review.coreboot.org/c/coreboot/+/55796/comment/e1d349b5_24864173
PS1, Line 115: _bootblock
> Hrmm, what would it take to use arch/x86/bootblock.ld? It looks like we just need a KCONFIG to remove the .id/.fit pointer
If there is nothing in those sections that should work too, so only conditionally include id.S. Fit has already been moved out.
https://review.coreboot.org/c/coreboot/+/55796/comment/e537ee8f_d98a9597
PS1, Line 124: 64
> Why the extra 64?
ALIGN(x) aligns downwards but we are aligning the bootblock to the top, so some extra bytes appended help.
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Change subject: soc/intel/common: Add support to control coreboot and Intel SoC features
......................................................................
Patch Set 16:
(2 comments)
File src/soc/intel/common/basecode/debug/Kconfig:
https://review.coreboot.org/c/coreboot/+/61380/comment/dd4dcc8d_958f141c
PS14, Line 5: Driver to control run time features of Intel SoC & coreboot
> Sure, I will improve description.
Ack
File src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h:
https://review.coreboot.org/c/coreboot/+/61380/comment/ca9b594a_54596231
PS14, Line 3: RT
> Not required.
Ack
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Hello Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62715
to look at the new patch set (#3).
Change subject: soc/intel/common: Add support to control CSE firmware update
......................................................................
soc/intel/common: Add support to control CSE firmware update
The patch adds support to control CSE Lite firmware update dynamically.
BUG=b:153410586
TEST=Verified controlling CSE Lite firmware update dynamically on Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: I9f234b142191eb83137d5d83f21e890e1cb828ba
---
M src/soc/intel/common/basecode/debug/debug_feature.c
M src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h
M src/soc/intel/common/block/cse/cse_lite.c
3 files changed, 30 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/62715/3
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