coreboot-gerrit March 2022

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Change in coreboot[master]: soc/intel/(cnl, jsl, tgl): Enable SOC_INTEL_COMMON_BASECODE
by Sridhar Siricilla (Code Review) 22 Mar '22

22 Mar '22

Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62843 to look at the new patch set (#2). Change subject: soc/intel/(cnl, jsl, tgl): Enable SOC_INTEL_COMMON_BASECODE ...................................................................... soc/intel/(cnl, jsl, tgl): Enable SOC_INTEL_COMMON_BASECODE The patch SOC_INTEL_COMMON_BASECODE Kconfig for Comet Lake, Jasper Lake and Tiger Lake SoCs. It allows access to intelbasecode/debug_feature.h for Comet Lake, Jasper Lake and Tiger Lake SoCs. TEST=Build code for Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ie55ded673c8fa0edf2ca6789b15771bd2e56c95e --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/tigerlake/Kconfig 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/62843/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie55ded673c8fa0edf2ca6789b15771bd2e56c95e Gerrit-Change-Number: 62843 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Add support to control coreboot and Intel SoC features
by Sridhar Siricilla (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Nico Huber, Sridhar Siricilla, Patrick Rudolph. Hello build bot (Jenkins), Subrata Banik, Maulik V Vaghela, Rizwan Qureshi, Krishna P Bhat D, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61380 to look at the new patch set (#16). Change subject: soc/intel/common: Add support to control coreboot and Intel SoC features ...................................................................... soc/intel/common: Add support to control coreboot and Intel SoC features The patch adds a framework to control coreboot and Intel SoC features dynamically. BIOS reads control information from OEM Section in the Descriptor Region and control the developer selected features. With the feature, debug team can control the selected SoC and coreboot features without rebuilding coreboot. In order to enable the feature, SOC_INTEL_COMMON_BLOCK_DEBUG_FEATURE has to be selcted from mainboard. The OEM section starts from offset:0xf00 till end of the Descriptor Region(0xfff). BUG=b:153410586 BRANCH=None TEST=Verified CSE firmware update functionality on brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 --- M src/soc/intel/common/basecode/Kconfig A src/soc/intel/common/basecode/debug/Kconfig A src/soc/intel/common/basecode/debug/Makefile.inc A src/soc/intel/common/basecode/debug/debug_feature.c A src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h 5 files changed, 63 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/61380/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/61380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 Gerrit-Change-Number: 61380 Gerrit-PatchSet: 16 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/smmstore: Enable 4KiB blocks in SMMSTORE
by Patrick Rudolph (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Sean Rhodes, Arthur Heymans, Patrick Rudolph. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62990 ) Change subject: drivers/smmstore: Enable 4KiB blocks in SMMSTORE ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: See https://github.com/coreboot/coreboot/blob/1f54599b9875e0de80c8636626bdfbe01… Not sure what the minimum flash sector size is on AMD or older platforms. Maybe this can be gathered from Kconfig/bootmedia API? -- To view, visit https://review.coreboot.org/c/coreboot/+/62990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieeed9f5895b8ddde753ebf596b803e8f440d5b74 Gerrit-Change-Number: 62990 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 22 Mar 2022 11:59:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/smmstore: Enable 4KiB blocks in SMMSTORE
by Sean Rhodes (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Arthur Heymans, Patrick Rudolph. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62990 ) Change subject: drivers/smmstore: Enable 4KiB blocks in SMMSTORE ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > SMM_BLOCK_SIZE is the same size as the min common denominator for block erase size supported on flas […] It's this^ change, or this -https://github.com/StarLabsLtd/edk2/commit/e5033f0e9a01c2d4288370ef25cb12f2ee0a339e The suggestion came from Patrick, to avoid the edk2 patches. It does not break erasing. -- To view, visit https://review.coreboot.org/c/coreboot/+/62990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieeed9f5895b8ddde753ebf596b803e8f440d5b74 Gerrit-Change-Number: 62990 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 22 Mar 2022 11:52:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/smmstore: Enable 4KiB blocks in SMMSTORE
by Arthur Heymans (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Sean Rhodes, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62990 ) Change subject: drivers/smmstore: Enable 4KiB blocks in SMMSTORE ...................................................................... Patch Set 1: Code-Review-2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62990/comment/a0b5269a_cae91ee9 PS1, Line 9: Enable 4KiB blocks in SMMSTORE so that payloads such as edk2 don't : assert. What do you mean? Patchset: PS1: SMM_BLOCK_SIZE is the same size as the min common denominator for block erase size supported on flash chips by coreboot. Setting it smaller would break erasing. I also vaguely remember that 64K is what EDK2 expects/needs. -- To view, visit https://review.coreboot.org/c/coreboot/+/62990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieeed9f5895b8ddde753ebf596b803e8f440d5b74 Gerrit-Change-Number: 62990 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 22 Mar 2022 11:45:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp1_1: Fix code not working with strict-aliasing rules
by Patrick Rudolph (Code Review) 22 Mar '22

22 Mar '22

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62995 ) Change subject: drivers/intel/fsp1_1: Fix code not working with strict-aliasing rules ...................................................................... drivers/intel/fsp1_1: Fix code not working with strict-aliasing rules Change-Id: Ifc95a093cf86c834d63825bf76312ed21ec68215 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/intel/fsp1_1/hob.c 1 file changed, 5 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/62995/1 diff --git a/src/drivers/intel/fsp1_1/hob.c b/src/drivers/intel/fsp1_1/hob.c index 9a09cfd..076dd5f 100644 --- a/src/drivers/intel/fsp1_1/hob.c +++ b/src/drivers/intel/fsp1_1/hob.c @@ -257,21 +257,19 @@ */ void print_hob_type_structure(u16 hob_type, void *hob_list_ptr) { - u32 *current_hob; - u32 *next_hob = 0; - u8 last_hob = 0; + void *current_hob; u32 current_type; const char *current_type_str; - current_hob = hob_list_ptr; - /* * Print out HOBs of our desired type until * the end of the HOB list */ printk(BIOS_DEBUG, "\n=== FSP HOB Data Structure ===\n"); printk(BIOS_DEBUG, "%p: hob_list_ptr\n", hob_list_ptr); - do { + for (current_hob = hob_list_ptr; !END_OF_HOB_LIST(current_hob); + current_hob = GET_NEXT_HOB(current_hob)) { + EFI_HOB_GENERIC_HEADER *current_header_ptr = (EFI_HOB_GENERIC_HEADER *)current_hob; @@ -292,16 +290,6 @@ break; } } - - /* Check for end of HOB list */ - last_hob = END_OF_HOB_LIST(current_hob); - if (!last_hob) { - /* Get next HOB pointer */ - next_hob = GET_NEXT_HOB(current_hob); - - /* Start on next HOB */ - current_hob = next_hob; - } - } while (!last_hob); + } printk(BIOS_DEBUG, "=== End of FSP HOB Data Structure ===\n\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/62995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc95a093cf86c834d63825bf76312ed21ec68215 Gerrit-Change-Number: 62995 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: driver/wifi: Add _DSM method for DDRRFIM
by Varshit B Pandya (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Paul Menzel, Tim Wawrzynczak, Sugnan Prabhu S. Varshit B Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61020 ) Change subject: driver/wifi: Add _DSM method for DDRRFIM ...................................................................... Patch Set 23: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61020/comment/8aa44bf0_1ad34c30 PS22, Line 7: src/ > Please remove that from the prefix. Done https://review.coreboot.org/c/coreboot/+/61020/comment/d0d6b3f1_e5afb821 PS22, Line 9: coreboot needs to propagate the CnviDdrRfim value info of the feature : enable/disable state into the CNVi via the WiFi DSM ACPI object. > Why does coreboot need to do that? updated the commit msg https://review.coreboot.org/c/coreboot/+/61020/comment/ffdb0fd6_40981b83 PS22, Line 13: function > functions Done -- To view, visit https://review.coreboot.org/c/coreboot/+/61020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I217b736df3d4224a6732d1941a160abcddbd8f37 Gerrit-Change-Number: 61020 Gerrit-PatchSet: 23 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Tue, 22 Mar 2022 11:11:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: driver/wifi: Add _DSM method for DDRRFIM
by Varshit B Pandya (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Varshit B Pandya, Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak, Sugnan Prabhu S. Hello build bot (Jenkins), Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak, Rizwan Qureshi, Sugnan Prabhu S, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61020 to look at the new patch set (#23). Change subject: driver/wifi: Add _DSM method for DDRRFIM ...................................................................... driver/wifi: Add _DSM method for DDRRFIM coreboot needs to propagate the CnviDdrRfim value info of the feature enable/disable state into the CNVi via the WiFi DSM ACPI object. This will be consumed by the Wi-Fi driver and it will act according to CB enablement configuration. This patch adds _DSM method for that. Add support for following 2 functions in _DSM method - Function 0: Function Support Query Returns a bitmask of functions supported. - Function 3: RFI enablement 0 Feature Enable 1 Feature Disable BUG=b:201724512 TEST=Build, boot brya0 and dump SSDT entries Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method { ToBuffer (Arg0, Local0) If ((Local0 == ToUUID ("7266172c-220b-4b29-814f-75e4dd26b5fd"))) { ToInteger (Arg2, Local1) If ((Local1 == Zero)) { Return (Buffer (One) { 0x09 }) } If ((Local1 == One)){} If ((Local1 == 0x02)){} If ((Local1 == 0x03)) { Return (Zero) } Return (Buffer (One) { 0x00 }) } Return (Buffer (One) { 0x00 }) } Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I217b736df3d4224a6732d1941a160abcddbd8f37 --- M src/drivers/wifi/generic/acpi.c 1 file changed, 67 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/61020/23 -- To view, visit https://review.coreboot.org/c/coreboot/+/61020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I217b736df3d4224a6732d1941a160abcddbd8f37 Gerrit-Change-Number: 61020 Gerrit-PatchSet: 23 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: ec/google: Add PSRC and PBOK method
by Eric Lai (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Varshit B Pandya, Subrata Banik, Tim Wawrzynczak, Rizwan Qureshi. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62945 ) Change subject: ec/google: Add PSRC and PBOK method ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia536a9e1528f6e415247eca9ed2b0b685eb73196 Gerrit-Change-Number: 62945 Gerrit-PatchSet: 4 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Comment-Date: Tue, 22 Mar 2022 11:01:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: TEST: Drop UEFI_2_4_BINDING
by Patrick Rudolph (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Lee Leahy. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62993 ) Change subject: TEST: Drop UEFI_2_4_BINDING ...................................................................... TEST: Drop UEFI_2_4_BINDING See what breaks. Change-Id: Iedc4b082e850a31242208360a69b910d0df3191e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/intel/fsp1_1/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/62993/1 diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 3ab9096..4c02de3 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -3,7 +3,7 @@ config PLATFORM_USES_FSP1_1 bool depends on !VBOOT_STARTS_IN_BOOTBLOCK - select UEFI_2_4_BINDING + select UDK_2017_BINDING select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select MICROCODE_UPDATE_PRE_RAM help -- To view, visit https://review.coreboot.org/c/coreboot/+/62993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedc4b082e850a31242208360a69b910d0df3191e Gerrit-Change-Number: 62993 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit March 2022