coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: commonlib/bsd/helpers: Remove redundancy with libpayload defines
by Jakub Czapiga (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Jakub Czapiga, Tim Wawrzynczak. Hello build bot (Jenkins), Tim Wawrzynczak, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62921 to look at the new patch set (#3). Change subject: commonlib/bsd/helpers: Remove redundancy with libpayload defines ...................................................................... commonlib/bsd/helpers: Remove redundancy with libpayload defines Move STRINGIFY() from coreboot string.h to commonlib/bsd/helpers.h Remove redundant defines from libpayload.h and libpayloads' standard headers. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I3263b2aa7657759207bf6ffda750d839e741f99c --- M payloads/libpayload/drivers/video/graphics.c M payloads/libpayload/include/libpayload.h M payloads/libpayload/include/stddef.h M payloads/libpayload/include/stdlib.h M src/commonlib/bsd/include/commonlib/bsd/helpers.h M src/include/string.h 6 files changed, 8 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/62921/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3263b2aa7657759207bf6ffda750d839e741f99c Gerrit-Change-Number: 62921 Gerrit-PatchSet: 3 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: ec/starlabs/merlin: Add EC related files for Cezanne boards
by Sean Rhodes (Code Review) 22 Mar '22

22 Mar '22

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62994 to look at the new patch set (#3). Change subject: ec/starlabs/merlin: Add EC related files for Cezanne boards ...................................................................... ec/starlabs/merlin: Add EC related files for Cezanne boards Add EC memory layout and Q events for Cezanne based boards, "Byte" and "Fighter, which both use the ITE 5570E. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I3f837263d24e6b642cf33fd2995d8c90529706f6 --- A src/ec/starlabs/merlin/variants/cezanne/ecdefs.h A src/ec/starlabs/merlin/variants/cezanne/emem.asl A src/ec/starlabs/merlin/variants/cezanne/events.asl 3 files changed, 360 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/62994/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f837263d24e6b642cf33fd2995d8c90529706f6 Gerrit-Change-Number: 62994 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: ec/starlabs/merlin: Add EC related files for Cezanne boards
by Sean Rhodes (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Sean Rhodes. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62994 ) Change subject: ec/starlabs/merlin: Add EC related files for Cezanne boards ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/62994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f837263d24e6b642cf33fd2995d8c90529706f6 Gerrit-Change-Number: 62994 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Tue, 22 Mar 2022 15:43:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taniks: Increase TSR2 threshold from 40 °C to 70 °C
by Tim Wawrzynczak (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: YH Lin, Joey Peng. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62952 ) Change subject: mb/google/brya/var/taniks: Increase TSR2 threshold from 40 °C to 70 °C ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I567815782ece4ab7fcec7da6b787ee9eec27aba4 Gerrit-Change-Number: 62952 Gerrit-PatchSet: 3 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Tue, 22 Mar 2022 15:31:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/gimble: Include 4 new SPDs
by Tim Wawrzynczak (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: YH Lin, Furquan Shaikh, Angel Pons, Nick Vaccaro, Mark Hsieh, Zhuohao Lee, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62991 ) Change subject: mb/google/brya/var/gimble: Include 4 new SPDs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I143207cda066603051803b9008eb2e2364f16e46 Gerrit-Change-Number: 62991 Gerrit-PatchSet: 1 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 22 Mar 2022 15:28:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/kinox: Modify DDR4 to non-interleaved
by Felix Held (Code Review) 22 Mar '22

22 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62953 ) Change subject: mb/google/brya/var/kinox: Modify DDR4 to non-interleaved ...................................................................... mb/google/brya/var/kinox: Modify DDR4 to non-interleaved Kinox is designed to 8-layer PCB. In order to reduce the length of memory singals, the DDR4 is designed from interleaved to non-interleaved. BUG=b:210094309 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I03c6fcccf8b1646cec1a35cc1f9cbb1cfb942c4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62953 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao(a)google.com> --- M src/mainboard/google/brya/variants/kinox/Makefile.inc A src/mainboard/google/brya/variants/kinox/memory.c 2 files changed, 32 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Zhuohao Lee: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/kinox/Makefile.inc b/src/mainboard/google/brya/variants/kinox/Makefile.inc index 681c764..27174f4 100644 --- a/src/mainboard/google/brya/variants/kinox/Makefile.inc +++ b/src/mainboard/google/brya/variants/kinox/Makefile.inc @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c romstage-y += gpio.c +romstage-y += memory.c ramstage-y += gpio.c ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/kinox/memory.c b/src/mainboard/google/brya/variants/kinox/memory.c new file mode 100644 index 0000000..ad33e9c --- /dev/null +++ b/src/mainboard/google/brya/variants/kinox/memory.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/romstage.h> + +static const struct mb_cfg ddr4_mem_config = { + .type = MEM_TYPE_DDR4, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + + /* Baseboard Rcomp target values */ + .targets = {50, 20, 25, 25, 25}, + }, + + .ect = 1, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, + + .ddr_config = { + .dq_pins_interleaved = false, + }, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &ddr4_mem_config; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/62953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03c6fcccf8b1646cec1a35cc1f9cbb1cfb942c4e Gerrit-Change-Number: 62953 Gerrit-PatchSet: 4 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Add APIs to check CSE's write protection info
by Sridhar Siricilla (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62986 to look at the new patch set (#3). Change subject: soc/intel/common: Add APIs to check CSE's write protection info ...................................................................... soc/intel/common: Add APIs to check CSE's write protection info The patch add APIs to check CSE Region's write protection information. Also, adds helper functions to get the SPI controller's MMIO address to access to BIOS_GPR0 register. The BIOS_GPR0 indicates write and read protection details. During the coreboot image build, write protection is enabled for CSE RO. It is enabled through a Intel MFIT XML configuration. TEST=Verify write protection information of CSE Region Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: If1da0fc410a15996f2e139809f7652127ef8761b --- M src/soc/intel/common/block/include/intelblocks/spi.h M src/soc/intel/common/block/spi/spi.c 2 files changed, 95 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/62986/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1da0fc410a15996f2e139809f7652127ef8761b Gerrit-Change-Number: 62986 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/hatch: split up hatch and puff baseboards
by Matt DeVillier (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62970 to look at the new patch set (#2). Change subject: mb/google/hatch: split up hatch and puff baseboards ...................................................................... mb/google/hatch: split up hatch and puff baseboards The hatch and puff baseboards have diverged enough to where it makes more sense to split them into separate boards. Copy the mb/google/hatch directory into a new dir 'puff' and strip out all boards and items related to the hatch baseboard. Remove all puff-related items from the original hatch directory. Clean up and alphabetize Kconfig selections. Test: build and boot akemi hatch variant and wyvern puff variant. Change-Id: I8c7350f3afcff3ddefc6fa14054a3f9257568cd3 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name M src/mainboard/google/hatch/Makefile.inc R src/mainboard/google/hatch/chromeos-16MiB.fmd R src/mainboard/google/hatch/chromeos-32MiB.fmd R src/mainboard/google/hatch/romstage.c M src/mainboard/google/hatch/variants/baseboard/mainboard.c A src/mainboard/google/puff/Kconfig A src/mainboard/google/puff/Kconfig.name A src/mainboard/google/puff/Makefile.inc A src/mainboard/google/puff/board_info.txt A src/mainboard/google/puff/bootblock.c R src/mainboard/google/puff/chromeos-16MiB.fmd R src/mainboard/google/puff/chromeos-32MiB.fmd A src/mainboard/google/puff/chromeos.c A src/mainboard/google/puff/dsdt.asl A src/mainboard/google/puff/ec.c A src/mainboard/google/puff/ramstage.c R src/mainboard/google/puff/romstage.c A src/mainboard/google/puff/smihandler.c R src/mainboard/google/puff/variants/ambassador/Makefile.inc R src/mainboard/google/puff/variants/ambassador/gpio.c R src/mainboard/google/puff/variants/ambassador/include/variant/ec.h R src/mainboard/google/puff/variants/ambassador/include/variant/gpio.h R src/mainboard/google/puff/variants/ambassador/overridetree.cb A src/mainboard/google/puff/variants/baseboard/Makefile.inc A src/mainboard/google/puff/variants/baseboard/devicetree.cb A src/mainboard/google/puff/variants/baseboard/gpio.c A src/mainboard/google/puff/variants/baseboard/include/baseboard/acpi/dptf.asl A src/mainboard/google/puff/variants/baseboard/include/baseboard/ec.h A src/mainboard/google/puff/variants/baseboard/include/baseboard/gpio.h A src/mainboard/google/puff/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/puff/variants/baseboard/include/puff/ec.h A src/mainboard/google/puff/variants/baseboard/mainboard.c A src/mainboard/google/puff/variants/baseboard/memory.c R src/mainboard/google/puff/variants/dooly/Makefile.inc R src/mainboard/google/puff/variants/dooly/data.vbt R src/mainboard/google/puff/variants/dooly/gpio.c R src/mainboard/google/puff/variants/dooly/include/variant/ec.h R src/mainboard/google/puff/variants/dooly/include/variant/gpio.h R src/mainboard/google/puff/variants/dooly/overridetree.cb R src/mainboard/google/puff/variants/duffy/Makefile.inc R src/mainboard/google/puff/variants/duffy/data.vbt R src/mainboard/google/puff/variants/duffy/gpio.c R src/mainboard/google/puff/variants/duffy/include/variant/ec.h R src/mainboard/google/puff/variants/duffy/include/variant/gpio.h R src/mainboard/google/puff/variants/duffy/overridetree.cb R src/mainboard/google/puff/variants/faffy/Makefile.inc R src/mainboard/google/puff/variants/faffy/data.vbt R src/mainboard/google/puff/variants/faffy/gpio.c R src/mainboard/google/puff/variants/faffy/include/variant/ec.h R src/mainboard/google/puff/variants/faffy/include/variant/gpio.h R src/mainboard/google/puff/variants/faffy/overridetree.cb R src/mainboard/google/puff/variants/genesis/Makefile.inc R src/mainboard/google/puff/variants/genesis/gpio.c R src/mainboard/google/puff/variants/genesis/include/variant/ec.h R src/mainboard/google/puff/variants/genesis/include/variant/gpio.h R src/mainboard/google/puff/variants/genesis/overridetree.cb R src/mainboard/google/puff/variants/kaisa/Makefile.inc R src/mainboard/google/puff/variants/kaisa/data.vbt R src/mainboard/google/puff/variants/kaisa/gpio.c R src/mainboard/google/puff/variants/kaisa/include/variant/ec.h R src/mainboard/google/puff/variants/kaisa/include/variant/gpio.h R src/mainboard/google/puff/variants/kaisa/overridetree.cb R src/mainboard/google/puff/variants/moonbuggy/Makefile.inc R src/mainboard/google/puff/variants/moonbuggy/gpio.c R src/mainboard/google/puff/variants/moonbuggy/include/variant/ec.h R src/mainboard/google/puff/variants/moonbuggy/include/variant/gpio.h R src/mainboard/google/puff/variants/moonbuggy/overridetree.cb A src/mainboard/google/puff/variants/mushu/Makefile.inc A src/mainboard/google/puff/variants/mushu/data.vbt A src/mainboard/google/puff/variants/mushu/gpio.c A src/mainboard/google/puff/variants/mushu/include/variant/acpi/dptf.asl A src/mainboard/google/puff/variants/mushu/include/variant/ec.h A src/mainboard/google/puff/variants/mushu/include/variant/gpio.h A src/mainboard/google/puff/variants/mushu/overridetree.cb A src/mainboard/google/puff/variants/mushu/ramstage.c R src/mainboard/google/puff/variants/noibat/Makefile.inc R src/mainboard/google/puff/variants/noibat/data.vbt R src/mainboard/google/puff/variants/noibat/gpio.c R src/mainboard/google/puff/variants/noibat/include/variant/ec.h R src/mainboard/google/puff/variants/noibat/include/variant/gpio.h R src/mainboard/google/puff/variants/noibat/overridetree.cb R src/mainboard/google/puff/variants/puff/Makefile.inc R src/mainboard/google/puff/variants/puff/data.vbt R src/mainboard/google/puff/variants/puff/gpio.c R src/mainboard/google/puff/variants/puff/include/variant/ec.h R src/mainboard/google/puff/variants/puff/include/variant/gpio.h R src/mainboard/google/puff/variants/puff/overridetree.cb R src/mainboard/google/puff/variants/scout/Makefile.inc R src/mainboard/google/puff/variants/scout/gpio.c R src/mainboard/google/puff/variants/scout/include/variant/ec.h R src/mainboard/google/puff/variants/scout/include/variant/gpio.h R src/mainboard/google/puff/variants/scout/overridetree.cb R src/mainboard/google/puff/variants/wyvern/Makefile.inc R src/mainboard/google/puff/variants/wyvern/data.vbt R src/mainboard/google/puff/variants/wyvern/gpio.c R src/mainboard/google/puff/variants/wyvern/include/variant/ec.h R src/mainboard/google/puff/variants/wyvern/include/variant/gpio.h R src/mainboard/google/puff/variants/wyvern/overridetree.cb 100 files changed, 2,285 insertions(+), 289 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/62970/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c7350f3afcff3ddefc6fa14054a3f9257568cd3 Gerrit-Change-Number: 62970 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/smmstore: Enable 4KiB blocks in SMMSTORE
by Sean Rhodes (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Patrick Rudolph, Arthur Heymans. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62990 ) Change subject: drivers/smmstore: Enable 4KiB blocks in SMMSTORE ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > What do you mean? Are there hardcoded assumptions when building the manifest about the memory mapping? The IFD and Manifest are made by FIT, there isn't a mechanism to say "use this IFD". Changing the IFD isn't practical anyway for systems that already exist in the wild. -- To view, visit https://review.coreboot.org/c/coreboot/+/62990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieeed9f5895b8ddde753ebf596b803e8f440d5b74 Gerrit-Change-Number: 62990 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 22 Mar 2022 14:56:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/smmstore: Enable 4KiB blocks in SMMSTORE
by Arthur Heymans (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Sean Rhodes, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62990 ) Change subject: drivers/smmstore: Enable 4KiB blocks in SMMSTORE ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Sorry dude, the logic is lost on me. If we don't change any defaults, someone selects an option that breaks something because they haven't read up on it, it's trial and error anyway - they'd just unselect it... No I disagree. Bad ports are like that. It's not because for some bad platforms the myriad of options allows for some broken combinations that this a good idea to introduce motr options like that. Ideally you want to have features exposed in menuconfig and sometimes alternative codepaths. What you don't want to expose are implementation details. > > > Have you tried the following using native coreboot tools to edit the layout? > No, as it would break the manifest. What do you mean? Are there hardcoded assumptions when building the manifest about the memory mapping? -- To view, visit https://review.coreboot.org/c/coreboot/+/62990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieeed9f5895b8ddde753ebf596b803e8f440d5b74 Gerrit-Change-Number: 62990 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 22 Mar 2022 14:52:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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coreboot-gerrit March 2022