coreboot-gerrit March 2022

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Change in coreboot[master]: libpayload/vboot: Fix include paths fixup macro
by Jakub Czapiga (Code Review) 22 Mar '22

22 Mar '22

Jakub Czapiga has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63002 ) Change subject: libpayload/vboot: Fix include paths fixup macro ...................................................................... libpayload/vboot: Fix include paths fixup macro Include paths fixup macro for vboot was broken and was adding unnecessary prefix to paths from $(coreboottop). This patch adds correct filters ti fix this behavior. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I264e715fa879a4e56b6e5f5423916298e8780a2b --- M payloads/libpayload/vboot/Makefile.inc 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/63002/1 diff --git a/payloads/libpayload/vboot/Makefile.inc b/payloads/libpayload/vboot/Makefile.inc index bd1afa8..6b6ae9d 100644 --- a/payloads/libpayload/vboot/Makefile.inc +++ b/payloads/libpayload/vboot/Makefile.inc @@ -8,10 +8,11 @@ tlcl-objs += $(TLCL_LIB) kconfig-to-binary=$(if $(strip $(1)),1,0) -vboot-fixup-includes = $(patsubst -I%,-I$(top)/%,\ +vboot-fixup-includes = $(filter -I$(coreboottop)/%, $(1)) \ + $(patsubst -I%,-I$(top)/%,\ $(patsubst include/%.h,$(top)/include/%.h,\ - $(filter-out -I$(obj),$(1)))) - + $(filter-out -I$(obj),\ + $(filter-out -I$(coreboottop)%,$(1))))) ifeq ($(CONFIG_LP_ARCH_MOCK),) VBOOT_CFLAGS += $(call vboot-fixup-includes,$(CFLAGS)) VBOOT_CFLAGS += -I$(abspath $(obj)) -- To view, visit https://review.coreboot.org/c/coreboot/+/63002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I264e715fa879a4e56b6e5f5423916298e8780a2b Gerrit-Change-Number: 63002 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common: move FCH IOAPIC and HPET init from SMBUs to LPC device
by Marshall Dawson (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58334 ) Change subject: soc/amd/common: move FCH IOAPIC and HPET init from SMBUs to LPC device ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I585afd463c1c00cd87ced0617e7802503c5deba5 Gerrit-Change-Number: 58334 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 22 Mar 2022 16:56:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/brya0: Replace amp max98357 with max98360
by Amanda Hwang (Code Review) 22 Mar '22

22 Mar '22

Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62998 ) Change subject: mb/google/brya/var/brya0: Replace amp max98357 with max98360 ...................................................................... mb/google/brya/var/brya0: Replace amp max98357 with max98360 Based on Brya EVT schametic, replace audio amp max98357 with max98360. Add a new audio FW_CONFIG field to support ALC5682I+MAX98360. BUG=b:224423056 BRANCH=firmware-brya-14505.B TEST=dmidecode -t 11 Change-Id: I3033e31cf5c2dade02dc19531f5e5365eeeb7a78 Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/brya0/fw_config.c M src/mainboard/google/brya/variants/brya0/overridetree.cb 2 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/62998/1 diff --git a/src/mainboard/google/brya/variants/brya0/fw_config.c b/src/mainboard/google/brya/variants/brya0/fw_config.c index 17d284a..e1c6f89 100644 --- a/src/mainboard/google/brya/variants/brya0/fw_config.c +++ b/src/mainboard/google/brya/variants/brya0/fw_config.c @@ -126,5 +126,10 @@ printk(BIOS_INFO, "Configure audio over I2S with ALC1019 NAU88L25B.\n"); enable_i2s(); } + + if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S_AMP_SSP2))) { + printk(BIOS_INFO, "Configure audio over I2S with MAX98360 ALC5682I.\n"); + enable_i2s(); + } } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 0f1c693..0b9e756 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -17,6 +17,7 @@ option MAX98373_ALC5682_SNDW 2 option MAX98373_NAU88L25B_I2S 3 option ALC1019_NAU88L25B_I2S 4 + option MAX98360_ALC5682I_I2S_AMP_SSP2 5 end field DB_LTE 11 12 option LTE_ABSENT 0 @@ -254,6 +255,7 @@ register "property_list[0].integer" = "1" device i2c 1a on probe AUDIO MAX98357_ALC5682I_I2S + probe AUDIO MAX98360_ALC5682I_I2S_AMP_SSP2 end end chip drivers/i2c/nau8825 @@ -611,6 +613,16 @@ end end + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "sdmode_delay" = "5" + device generic 0 on + probe AUDIO MAX98360_ALC5682I_I2S_AMP_SSP2 + end + end + chip drivers/intel/soundwire device generic 0 on probe AUDIO MAX98373_ALC5682_SNDW -- To view, visit https://review.coreboot.org/c/coreboot/+/62998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3033e31cf5c2dade02dc19531f5e5365eeeb7a78 Gerrit-Change-Number: 62998 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/banshee: Add mic mute switch setting
by Tim Wawrzynczak (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Frank Wu, John Su, YH Lin, Dtrain Hsu, Ian Feng, Paul Menzel, Nick Vaccaro, Eric Lai, Amanda Hwang, Ricky Chang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62804 ) Change subject: mb/google/brya/var/banshee: Add mic mute switch setting ...................................................................... Patch Set 7: (1 comment) File src/mainboard/google/brya/variants/banshee/overridetree.cb: https://review.coreboot.org/c/coreboot/+/62804/comment/a2df4e84_4d1b266d PS5, Line 328: register "privacy_gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_F19)" > The GPP_F22 is active high from HW's feedback. Changing the privacy GPIO polarity is unrelated to the mic mute switch, it should go in a separate CL -- To view, visit https://review.coreboot.org/c/coreboot/+/62804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f7176afbd64f7c080f02369f195043a2df88e5d Gerrit-Change-Number: 62804 Gerrit-PatchSet: 7 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: Ricky Chang <rickytlchang(a)google.com> Gerrit-Comment-Date: Tue, 22 Mar 2022 16:25:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/spd_tools: Add support for exclusive IDs
by Karthik Ramasubramanian (Code Review) 22 Mar '22

22 Mar '22

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62905 ) Change subject: util/spd_tools: Add support for exclusive IDs ...................................................................... util/spd_tools: Add support for exclusive IDs Currently memory parts that use the same SPD are assigned the same ID by spd_tools. This commit adds support for exclusive IDs. When given an exclusive ID a memory part will not share its ID with other parts unless they also have the same exclusive ID. BUG=b:225161910 TEST=Ran part_id_gen and checked that exclusive IDs work correctly and that the current behavior still works in their abscence. Signed-off-by: Robert Zieba <robertzieba(a)google.com> Change-Id: Ife5afe32337f69bc06451ce16238c7a83bc983c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62905 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M util/spd_tools/README.md M util/spd_tools/src/part_id_gen/part_id_gen.go 2 files changed, 62 insertions(+), 17 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/util/spd_tools/README.md b/util/spd_tools/README.md index 3a1342c..01bc417 100644 --- a/util/spd_tools/README.md +++ b/util/spd_tools/README.md @@ -459,10 +459,14 @@ * The memory technology used by the board, e.g. lp4x. * The path to the directory where the generated Makefile.inc should be placed. * A CSV file containing a list of the memory parts used by the board, with an - optional fixed ID for each part. NOTE: Only assign a fixed ID if required - for legacy reasons. +* optional fixed or exclusive ID for each part. A fixed ID is simply an integer +* and it ensure that part (and any that share the same SPD) will be assigned +* that ID. An exclusive ID is prefixed with `*` and ensures that only parts with +* the same exclusive ID will be assigned that ID, even if they would otherwise +* share the same ID. +* NOTE: Only assign a fixed/exclusive ID if required for legacy reasons. -Example of a CSV file using fixed IDs: +Example of a CSV file using fixed and exclusive IDs: ``` K4AAG165WA-BCWE,1 @@ -470,13 +474,15 @@ MT40A1G16KD-062E:E K4A8G165WC-BCWE H5AN8G6NDJR-XNC,8 -H5ANAG6NCMR-XNC +H5ANAG6NCMR-XNC,*9 ``` Explanation: This will ensure that the SPDs for K4AAG165WA-BCWE and -H5AN8G6NDJR-XNC are assigned to IDs 1 and 8 respectively. The SPDs for all other -memory parts will be assigned to the first compatible ID. Assigning fixed IDs -may result in duplicate SPD entries or gaps in the ID mapping. +H5AN8G6NDJR-XNC are assigned to IDs 1 and 8 respectively. H5ANAG6NCMR-XNC +will be assigned ID 9 and no other part will be assigned ID 9 even if it +shares the same SPD. The SPDs for all other memory parts will be assigned to +the first compatible ID. Assigning fixed/exclusive IDs may result in duplicate +SPD entries or gaps in the ID mapping. ### Output diff --git a/util/spd_tools/src/part_id_gen/part_id_gen.go b/util/spd_tools/src/part_id_gen/part_id_gen.go index 750b825..65e07f4 100644 --- a/util/spd_tools/src/part_id_gen/part_id_gen.go +++ b/util/spd_tools/src/part_id_gen/part_id_gen.go @@ -93,9 +93,18 @@ return nil } +type mappingType int + +const ( + Auto mappingType = iota + Fixed + Exclusive +) + type usedPart struct { partName string index int + mapping mappingType } func readPlatformsManifest(memTech string) (map[string]string, error) { @@ -174,16 +183,28 @@ } if len(fields) == 1 { - parts = append(parts, usedPart{fields[0], -1}) + parts = append(parts, usedPart{fields[0], -1, Auto}) } else if len(fields) == 2 { - assignedId, err := strconv.Atoi(fields[1]) + var mapping = Auto + var assignedId = -1 + var err error = nil + + if len(fields[1]) >= 2 && fields[1][0] == '*' { + // Exclusive mapping + mapping = Exclusive + assignedId, err = strconv.Atoi(fields[1][1:]) + } else { + mapping = Fixed + assignedId, err = strconv.Atoi(fields[1]) + } + if err != nil { return nil, err } if assignedId > MaxMemoryId || assignedId < 0 { return nil, fmt.Errorf("Out of bounds assigned id %d for part %s", assignedId, fields[0]) } - parts = append(parts, usedPart{fields[0], assignedId}) + parts = append(parts, usedPart{fields[0], assignedId, mapping}) } else { return nil, fmt.Errorf("mem_parts_used_file file is incorrectly formatted") } @@ -245,7 +266,7 @@ } func getFileHeader() string { - return `# SPDX-License-Identifier: GPL-2.0-or-later + return `# SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: ` + fmt.Sprintf("# %s\n\n", strings.Join(os.Args[0:], " ")) @@ -262,6 +283,7 @@ */ func genPartIdInfo(parts []usedPart, partToSPDMap map[string]string, SPDToIndexMap map[string]int, makefileDirName string) ([]partIds, error) { partIdList := []partIds{} + assignedMapping := []mappingType{} var s string // Assign parts with fixed ids first @@ -280,19 +302,34 @@ return nil, fmt.Errorf("Failed to find part ", p.partName, " in SPD Manifest. Please add the part to global part list and regenerate SPD Manifest") } - // Extend partIdList with empty entries if needed + // Extend partIdList and assignedMapping with empty entries if needed for i := len(partIdList) - 1; i < p.index; i++ { partIdList = append(partIdList, partIds{}) + assignedMapping = append(assignedMapping, Auto) } - if partIdList[p.index].SPDFileName != "" { - return nil, fmt.Errorf("Part ", p.partName, " is assigned to an already assigned ID ", p.index) + // Only allow parts with the same index if they share the same SPD + assignedSPD := partIdList[p.index].SPDFileName + if assignedSPD != "" && assignedSPD != partToSPDMap[p.partName] { + return nil, fmt.Errorf("ID %d is already assigned to %s, conflicting with %s(%s)", p.index, assignedSPD, p.partName, SPDFileName) } - partIdList[p.index] = partIds{SPDFileName: SPDFileName, memParts: p.partName} + mapping := assignedMapping[p.index] + if (mapping == Fixed && p.mapping == Exclusive) || (mapping == Exclusive && p.mapping == Fixed) { + return nil, fmt.Errorf("Exclusive/non-exclusive conflict in assigning %s to ID %d", p.partName, p.index) + } else { + assignedMapping[p.index] = p.mapping + } + + if partIdList[p.index].memParts == "" { + partIdList[p.index] = partIds{SPDFileName: SPDFileName, memParts: p.partName} + } else { + partIdList[p.index].memParts += ", " + p.partName + } // SPDToIndexMap should point to first assigned index in the used part list - if SPDToIndexMap[SPDFileName] < 0 { + // Exclusive entries don't update the map because they're not valid for auto assigning + if SPDToIndexMap[SPDFileName] < 0 && p.mapping != Exclusive { SPDToIndexMap[SPDFileName] = p.index } } @@ -317,7 +354,8 @@ } index := SPDToIndexMap[SPDFileName] - if index != -1 { + // Only Exclusive mappings don't allow automatic assigning of parts + if index != -1 && assignedMapping[index] != Exclusive { partIdList[index].memParts += ", " + p.partName appendPartIdInfo(&s, p.partName, index) continue @@ -338,6 +376,7 @@ return nil, fmt.Errorf("Maximum part ID %d exceeded.", MaxMemoryId) } partIdList = append(partIdList, partIds{}) + assignedMapping = append(assignedMapping, Auto) } SPDToIndexMap[SPDFileName] = index -- To view, visit https://review.coreboot.org/c/coreboot/+/62905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife5afe32337f69bc06451ce16238c7a83bc983c8 Gerrit-Change-Number: 62905 Gerrit-PatchSet: 9 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/banshee: Add mic mute switch setting
by Frank Wu (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: John Su, YH Lin, Dtrain Hsu, Ian Feng, Paul Menzel, Tim Wawrzynczak, Nick Vaccaro, Eric Lai, Amanda Hwang, Ricky Chang. Frank Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62804 ) Change subject: mb/google/brya/var/banshee: Add mic mute switch setting ...................................................................... Patch Set 7: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62804/comment/2daa832b_e7dc8017 PS5, Line 13: TEST=emerge-brya coreboot chromeos-bootimage > any evtest log? localhost ~ # crossystem | grep fwid fwid = Google_Banshee.14505.42.2022_03_22_1356 # [RO/str] Active firmware ID ro_fwid = Google_Banshee.14505.42.2022_03_22_1356 # [RO/str] Read-only firmware ID localhost ~ # evtest No device specified, trying to scan all of /dev/input/event* Available devices: /dev/input/event0: Lid Switch /dev/input/event1: Power Button /dev/input/event2: AT Translated Set 2 keyboard /dev/input/event3: cros_ec_buttons /dev/input/event4: mic_mute_switch /dev/input/event5: PNP0C50:00 093A:0274 Mouse /dev/input/event6: PNP0C50:00 093A:0274 Touchpad /dev/input/event7: Lite-On Technology Corp. ThinkPad USB Keyboard with TrackPoint /dev/input/event8: Lite-On Technology Corp. ThinkPad USB Keyboard with TrackPoint Mouse /dev/input/event9: Lite-On Technology Corp. ThinkPad USB Keyboard with TrackPoint System Control /dev/input/event10: Lite-On Technology Corp. ThinkPad USB Keyboard with TrackPoint Consumer Control /dev/input/event11: sof-rt5682 Headset Jack /dev/input/event12: sof-rt5682 HDMI/DP,pcm=2 /dev/input/event13: sof-rt5682 HDMI/DP,pcm=3 /dev/input/event14: sof-rt5682 HDMI/DP,pcm=4 /dev/input/event15: sof-rt5682 HDMI/DP,pcm=5 Select the device event number [0-15]: 4 Input driver version is 1.0.1 Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100 Input device name: "mic_mute_switch" Supported events: Event type 0 (EV_SYN) Event type 5 (EV_SW) Event code 14 (SW_MUTE_DEVICE) state 1 Properties: Testing ... (interrupt to exit) Event: time 1647939954.639995, type 5 (EV_SW), code 14 (SW_MUTE_DEVICE), value 0 Event: time 1647939954.639995, -------------- SYN_REPORT ------------ Event: time 1647939954.648152, type 5 (EV_SW), code 14 (SW_MUTE_DEVICE), value 1 Event: time 1647939954.648152, -------------- SYN_REPORT ------------ Event: time 1647939954.841961, type 5 (EV_SW), code 14 (SW_MUTE_DEVICE), value 0 Event: time 1647939954.841961, -------------- SYN_REPORT ------------ Event: time 1647939954.845026, type 5 (EV_SW), code 14 (SW_MUTE_DEVICE), value 1 Event: time 1647939954.845026, -------------- SYN_REPORT ------------ Event: time 1647939954.920548, type 5 (EV_SW), code 14 (SW_MUTE_DEVICE), value 0 Event: time 1647939954.920548, -------------- SYN_REPORT ------------ Event: time 1647939954.922793, type 5 (EV_SW), code 14 (SW_MUTE_DEVICE), value 1 Event: time 1647939954.922793, -------------- SYN_REPORT ------------ Event: time 1647939957.664608, type 5 (EV_SW), code 14 (SW_MUTE_DEVICE), value 0 Event: time 1647939957.664608, -------------- SYN_REPORT ------------ File src/mainboard/google/brya/variants/banshee/overridetree.cb: https://review.coreboot.org/c/coreboot/+/62804/comment/71ce7f32_684ed9f4 PS5, Line 328: register "privacy_gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_F19)" > Is this intended? The GPP_F22 is active high from HW's feedback. -- To view, visit https://review.coreboot.org/c/coreboot/+/62804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f7176afbd64f7c080f02369f195043a2df88e5d Gerrit-Change-Number: 62804 Gerrit-PatchSet: 7 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: Ricky Chang <rickytlchang(a)google.com> Gerrit-Comment-Date: Tue, 22 Mar 2022 16:11:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/banshee: Add mic mute switch setting
by Frank Wu (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: John Su, YH Lin, Dtrain Hsu, Ian Feng, Paul Menzel, Tim Wawrzynczak, Nick Vaccaro, Amanda Hwang, Ricky Chang. Hello build bot (Jenkins), John Su, YH Lin, Dtrain Hsu, Ian Feng, Tim Wawrzynczak, Nick Vaccaro, Eric Lai, Amanda Hwang, Ricky Chang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62804 to look at the new patch set (#7). Change subject: mb/google/brya/var/banshee: Add mic mute switch setting ...................................................................... mb/google/brya/var/banshee: Add mic mute switch setting Using the GPP_F22 as mic mute switch based on the latest schematic. BUG=b:223737606, b:216110896 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage The mic_mute event is changed when the mic_mute GPIO pin is switched. Event: time 1647939954.639995, type 5 (EV_SW), code 14 (SW_MUTE_DEVICE), value 0 Event: time 1647939954.639995, -------------- SYN_REPORT ------------ Event: time 1647939954.648152, type 5 (EV_SW), code 14 (SW_MUTE_DEVICE), value 1 Event: time 1647939954.648152, -------------- SYN_REPORT ------------ Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: I6f7176afbd64f7c080f02369f195043a2df88e5d --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/banshee/gpio.c M src/mainboard/google/brya/variants/banshee/overridetree.cb 3 files changed, 15 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/62804/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/62804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f7176afbd64f7c080f02369f195043a2df88e5d Gerrit-Change-Number: 62804 Gerrit-PatchSet: 7 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: Ricky Chang <rickytlchang(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne: Turn off gpp clock request for disabled devices
by Felix Held (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Robert Zieba, Jason Glenesk, Raul Rangel, Martin L Roth, Marshall Dawson, Paul Menzel, Fred Reitberger, Rob Barnes, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61259 ) Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices ...................................................................... Patch Set 37: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c Gerrit-Change-Number: 61259 Gerrit-PatchSet: 37 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Martin L Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 22 Mar 2022 16:03:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Turn off gpp clock request for disabled devices
by Robert Zieba (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Robert Zieba, Jason Glenesk, Raul Rangel, Martin L Roth, Marshall Dawson, Paul Menzel, Fred Reitberger, Rob Barnes, Karthik Ramasubramanian. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Rob Barnes, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61259 to look at the new patch set (#37). Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices ...................................................................... soc/amd/cezanne: Turn off gpp clock request for disabled devices The current behavior does not actually check if a device is present before enabling the corresponding gpp_clkx_clock_request_mapping bits which may cause issues with L1SS. This change sets the corresponding gpp_clkx_clock_request_mapping to off if the corresponding device is disabled. BUG=b:202252869 TEST=Checked that value of GPP_CLK_CNTRL matched the expected value when devices are enabled/disabled, checked that physically removing a device that is marked as enabled also disables the corresponding clk req BRANCH=guybrush Signed-off-by: Robert Zieba <robertzieba(a)google.com> Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c --- M src/mainboard/amd/majolica/Makefile.inc M src/mainboard/google/guybrush/Makefile.inc M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/fch.c 4 files changed, 106 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/61259/37 -- To view, visit https://review.coreboot.org/c/coreboot/+/61259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c Gerrit-Change-Number: 61259 Gerrit-PatchSet: 37 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Martin L Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: ec/starlabs/merlin: Add EC related files for Cezanne boards
by Sean Rhodes (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Paul Menzel. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62994 ) Change subject: ec/starlabs/merlin: Add EC related files for Cezanne boards ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62994/comment/3ce764b7_f402acdd PS3, Line 9: Cezanne > AMD Cezanne Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f837263d24e6b642cf33fd2995d8c90529706f6 Gerrit-Change-Number: 62994 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 22 Mar 2022 15:57:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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